Started on HBridge power module

MLI/Modular/HBridgePowerModule/HBridgePowerModule.net

@@ -0,0 +1,286 @@
+(export (version D)
+  (design
+    (source C:/Development/MliHardware/MLI/Modular/HBridgePowerModule/HBridgePowerModule.sch)
+    (date "06/12/2017 15:59:43")
+    (tool "Eeschema 4.0.7")
+    (sheet (number 1) (name /) (tstamps /)
+      (title_block
+        (title "MLI HBridge Power Board")
+        (company "Enertechnos Ltd")
+        (rev "Rev 3")
+        (date 2017-12-06)
+        (source HBridgePowerModule.sch)
+        (comment (number 1) (value ""))
+        (comment (number 2) (value ""))
+        (comment (number 3) (value ""))
+        (comment (number 4) (value "For approval by Mansour"))))
+    (sheet (number 2) (name "/SinglePowerSwitch 1/") (tstamps /59AEDD49/)
+      (title_block
+        (title)
+        (company)
+        (rev)
+        (date)
+        (source SinglePowerSwitch.sch)
+        (comment (number 1) (value ""))
+        (comment (number 2) (value ""))
+        (comment (number 3) (value ""))
+        (comment (number 4) (value ""))))
+    (sheet (number 3) (name "/SinglePowerSwitch 2/") (tstamps /59AEEDCB/)
+      (title_block
+        (title)
+        (company)
+        (rev)
+        (date)
+        (source SinglePowerSwitch.sch)
+        (comment (number 1) (value ""))
+        (comment (number 2) (value ""))
+        (comment (number 3) (value ""))
+        (comment (number 4) (value ""))))
+    (sheet (number 4) (name "/SinglePowerSwitch 3/") (tstamps /59AEEFC6/)
+      (title_block
+        (title)
+        (company)
+        (rev)
+        (date)
+        (source SinglePowerSwitch.sch)
+        (comment (number 1) (value ""))
+        (comment (number 2) (value ""))
+        (comment (number 3) (value ""))
+        (comment (number 4) (value ""))))
+    (sheet (number 5) (name "/SinglePowerSwitch 4/") (tstamps /59AEEFCD/)
+      (title_block
+        (title)
+        (company)
+        (rev)
+        (date)
+        (source SinglePowerSwitch.sch)
+        (comment (number 1) (value ""))
+        (comment (number 2) (value ""))
+        (comment (number 3) (value ""))
+        (comment (number 4) (value "")))))
+  (components
+    (comp (ref J1)
+      (value RJ45)
+      (footprint PartsLibraries:RJ45)
+      (libsource (lib OAE.Parts) (part RJ45))
+      (sheetpath (names /) (tstamps /))
+      (tstamp 59AED755))
+    (comp (ref J6)
+      (value AC_OUT)
+      (footprint PartsLibraries:PowerConnectorRound)
+      (libsource (lib conn) (part Conn_01x01))
+      (sheetpath (names /) (tstamps /))
+      (tstamp 59AEFF90))
+    (comp (ref J7)
+      (value AC_OUT)
+      (footprint PartsLibraries:PowerConnectorRound)
+      (libsource (lib conn) (part Conn_01x01))
+      (sheetpath (names /) (tstamps /))
+      (tstamp 59AFA697))
+    (comp (ref J2)
+      (value POS_IN)
+      (footprint PartsLibraries:PowerConnectorRound)
+      (libsource (lib conn) (part Conn_01x01))
+      (sheetpath (names /) (tstamps /))
+      (tstamp 5A28227C))
+    (comp (ref J3)
+      (value NEG_IN)
+      (footprint PartsLibraries:PowerConnectorRound)
+      (libsource (lib conn) (part Conn_01x01))
+      (sheetpath (names /) (tstamps /))
+      (tstamp 5A28246C))
+    (comp (ref Q1)
+      (value RFP12N10L)
+      (footprint TO_SOT_Packages_THT:TO-247_TO-3P_Vertical)
+      (datasheet https://componentsearchengine.com/Datasheets/2/RFP12N10L.pdf)
+      (fields
+        (field (name Description) "N-channel logicFET,RFP12N10L 12A 100V")
+        (field (name Manufacturer_Name) "Fairchild Semiconductor")
+        (field (name Manufacturer_Part_Number) RFP12N10L)
+        (field (name Supplier_Name) RS)
+        (field (name "RS Part Number") 0295703)
+        (field (name Height) 4.7))
+      (libsource (lib OAE.Parts) (part RFP12N10L))
+      (sheetpath (names "/SinglePowerSwitch 1/") (tstamps /59AEDD49/))
+      (tstamp 59AEE014))
+    (comp (ref C1)
+      (value C)
+      (footprint PartsLibraries:CP_Radial_D5.0mm_P2.50mm)
+      (libsource (lib device) (part C))
+      (sheetpath (names "/SinglePowerSwitch 1/") (tstamps /59AEDD49/))
+      (tstamp 59AEE01D))
+    (comp (ref Q2)
+      (value RFP12N10L)
+      (footprint TO_SOT_Packages_THT:TO-247_TO-3P_Vertical)
+      (datasheet https://componentsearchengine.com/Datasheets/2/RFP12N10L.pdf)
+      (fields
+        (field (name Description) "N-channel logicFET,RFP12N10L 12A 100V")
+        (field (name Manufacturer_Name) "Fairchild Semiconductor")
+        (field (name Manufacturer_Part_Number) RFP12N10L)
+        (field (name Supplier_Name) RS)
+        (field (name "RS Part Number") 0295703)
+        (field (name Height) 4.7))
+      (libsource (lib OAE.Parts) (part RFP12N10L))
+      (sheetpath (names "/SinglePowerSwitch 2/") (tstamps /59AEEDCB/))
+      (tstamp 59AEE014))
+    (comp (ref C2)
+      (value C)
+      (footprint PartsLibraries:CP_Radial_D5.0mm_P2.50mm)
+      (libsource (lib device) (part C))
+      (sheetpath (names "/SinglePowerSwitch 2/") (tstamps /59AEEDCB/))
+      (tstamp 59AEE01D))
+    (comp (ref Q3)
+      (value RFP12N10L)
+      (footprint TO_SOT_Packages_THT:TO-247_TO-3P_Vertical)
+      (datasheet https://componentsearchengine.com/Datasheets/2/RFP12N10L.pdf)
+      (fields
+        (field (name Description) "N-channel logicFET,RFP12N10L 12A 100V")
+        (field (name Manufacturer_Name) "Fairchild Semiconductor")
+        (field (name Manufacturer_Part_Number) RFP12N10L)
+        (field (name Supplier_Name) RS)
+        (field (name "RS Part Number") 0295703)
+        (field (name Height) 4.7))
+      (libsource (lib OAE.Parts) (part RFP12N10L))
+      (sheetpath (names "/SinglePowerSwitch 3/") (tstamps /59AEEFC6/))
+      (tstamp 59AEE014))
+    (comp (ref C3)
+      (value C)
+      (footprint PartsLibraries:CP_Radial_D5.0mm_P2.50mm)
+      (libsource (lib device) (part C))
+      (sheetpath (names "/SinglePowerSwitch 3/") (tstamps /59AEEFC6/))
+      (tstamp 59AEE01D))
+    (comp (ref Q4)
+      (value RFP12N10L)
+      (footprint TO_SOT_Packages_THT:TO-247_TO-3P_Vertical)
+      (datasheet https://componentsearchengine.com/Datasheets/2/RFP12N10L.pdf)
+      (fields
+        (field (name Description) "N-channel logicFET,RFP12N10L 12A 100V")
+        (field (name Manufacturer_Name) "Fairchild Semiconductor")
+        (field (name Manufacturer_Part_Number) RFP12N10L)
+        (field (name Supplier_Name) RS)
+        (field (name "RS Part Number") 0295703)
+        (field (name Height) 4.7))
+      (libsource (lib OAE.Parts) (part RFP12N10L))
+      (sheetpath (names "/SinglePowerSwitch 4/") (tstamps /59AEEFCD/))
+      (tstamp 59AEE014))
+    (comp (ref C4)
+      (value C)
+      (footprint PartsLibraries:CP_Radial_D5.0mm_P2.50mm)
+      (libsource (lib device) (part C))
+      (sheetpath (names "/SinglePowerSwitch 4/") (tstamps /59AEEFCD/))
+      (tstamp 59AEE01D)))
+  (libparts
+    (libpart (lib device) (part C)
+      (description "Unpolarized capacitor")
+      (footprints
+        (fp C_*))
+      (fields
+        (field (name Reference) C)
+        (field (name Value) C))
+      (pins
+        (pin (num 1) (name ~) (type passive))
+        (pin (num 2) (name ~) (type passive))))
+    (libpart (lib conn) (part Conn_01x01)
+      (description "Generic connector, single row, 01x01")
+      (docs ~)
+      (footprints
+        (fp Connector*:*_??x*mm*)
+        (fp Connector*:*1x??x*mm*)
+        (fp Pin?Header?Straight?1X*)
+        (fp Pin?Header?Angled?1X*)
+        (fp Socket?Strip?Straight?1X*)
+        (fp Socket?Strip?Angled?1X*))
+      (fields
+        (field (name Reference) J)
+        (field (name Value) Conn_01x01))
+      (pins
+        (pin (num 1) (name Pin_1) (type passive))))
+    (libpart (lib OAE.Parts) (part RFP12N10L)
+      (fields
+        (field (name Reference) Q)
+        (field (name Value) RFP12N10L)
+        (field (name Footprint) TO254P470X1016X2167-3P)
+        (field (name Datasheet) https://www.fairchildsemi.com/datasheets/RF/RFP12N10L.pdf)
+        (field (name Description) "N-channel logicFET,RFP12N10L 12A 100V")
+        (field (name Manufacturer_Name) "Fairchild Semiconductor")
+        (field (name Manufacturer_Part_Number) RFP12N10L)
+        (field (name Supplier_Name) RS)
+        (field (name "RS Part Number") 0295703)
+        (field (name Height) 4.7))
+      (pins
+        (pin (num 1) (name G) (type unspc))
+        (pin (num 2) (name D) (type unspc))
+        (pin (num 3) (name S) (type unspc))
+        (pin (num 4) (name "D__(TAB)") (type unspc))))
+    (libpart (lib OAE.Parts) (part RJ45)
+      (description "RJ45 connector")
+      (fields
+        (field (name Reference) J)
+        (field (name Value) RJ45))
+      (pins
+        (pin (num 1) (name ~) (type passive))
+        (pin (num 2) (name ~) (type passive))
+        (pin (num 3) (name ~) (type passive))
+        (pin (num 4) (name ~) (type passive))
+        (pin (num 5) (name ~) (type passive))
+        (pin (num 6) (name ~) (type passive))
+        (pin (num 7) (name ~) (type passive))
+        (pin (num 8) (name ~) (type passive)))))
+  (libraries
+    (library (logical OAE.Parts)
+      (uri C:\Development\multilevelinverter\Hardware\PartsLibraries\OAE.Parts.lib))
+    (library (logical device)
+      (uri "C:\\Program Files\\KiCad\\share\\kicad\\library\\device.lib"))
+    (library (logical conn)
+      (uri "C:\\Program Files\\KiCad\\share\\kicad\\library\\conn.lib")))
+  (nets
+    (net (code 1) (name "/SinglePowerSwitch 3/DRAIN")
+      (node (ref Q3) (pin 2))
+      (node (ref J3) (pin 1))
+      (node (ref C3) (pin 2))
+      (node (ref Q4) (pin 2))
+      (node (ref C4) (pin 2)))
+    (net (code 2) (name DRV_GATE_4)
+      (node (ref Q4) (pin 1))
+      (node (ref J1) (pin 2)))
+    (net (code 3) (name "Net-(J6-Pad1)")
+      (node (ref J6) (pin 1)))
+    (net (code 4) (name "Net-(J7-Pad1)")
+      (node (ref J7) (pin 1)))
+    (net (code 5) (name GND_ISO_3)
+      (node (ref C1) (pin 2))
+      (node (ref Q1) (pin 2))
+      (node (ref C3) (pin 1))
+      (node (ref Q3) (pin 3))
+      (node (ref J1) (pin 1)))
+    (net (code 6) (name GND_ISO_4)
+      (node (ref C2) (pin 2))
+      (node (ref Q2) (pin 2))
+      (node (ref C4) (pin 1))
+      (node (ref Q4) (pin 3))
+      (node (ref J1) (pin 4)))
+    (net (code 7) (name GND_ISO_1)
+      (node (ref J2) (pin 1))
+      (node (ref J1) (pin 5))
+      (node (ref J1) (pin 8))
+      (node (ref C2) (pin 1))
+      (node (ref C1) (pin 1))
+      (node (ref Q1) (pin 3))
+      (node (ref Q2) (pin 3)))
+    (net (code 8) (name DRV_GATE_2)
+      (node (ref Q2) (pin 1))
+      (node (ref J1) (pin 6)))
+    (net (code 9) (name DRV_GATE_1)
+      (node (ref Q1) (pin 1))
+      (node (ref J1) (pin 7)))
+    (net (code 10) (name DRV_GATE_3)
+      (node (ref Q3) (pin 1))
+      (node (ref J1) (pin 3)))
+    (net (code 11) (name "Net-(Q1-Pad4)")
+      (node (ref Q1) (pin 4)))
+    (net (code 12) (name "Net-(Q2-Pad4)")
+      (node (ref Q2) (pin 4)))
+    (net (code 13) (name "Net-(Q3-Pad4)")
+      (node (ref Q3) (pin 4)))
+    (net (code 14) (name "Net-(Q4-Pad4)")
+      (node (ref Q4) (pin 4)))))

MLI/Modular/HBridgePowerModule/HBridgePowerModule.pro

@@ -0,0 +1,71 @@
+update=06/12/2017 14:01:49
+version=1
+last_client=kicad
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[general]
+version=1
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=C:/Development/multilevelinverter/Hardware/PartsLibraries/OAE.Parts
+LibName2=power
+LibName3=device
+LibName4=transistors
+LibName5=conn
+LibName6=linear
+LibName7=regul
+LibName8=74xx
+LibName9=cmos4000
+LibName10=adc-dac
+LibName11=memory
+LibName12=xilinx
+LibName13=microcontrollers
+LibName14=dsp
+LibName15=microchip
+LibName16=analog_switches
+LibName17=motorola
+LibName18=texas
+LibName19=intel
+LibName20=audio
+LibName21=interface
+LibName22=digital-audio
+LibName23=philips
+LibName24=display
+LibName25=cypress
+LibName26=siliconi
+LibName27=opto
+LibName28=atmel
+LibName29=contrib
+LibName30=valves
+[schematic_editor]
+version=1
+PageLayoutDescrFile=
+PlotDirectoryName=
+SubpartIdSeparator=0
+SubpartFirstId=65
+NetFmtName=
+SpiceForceRefPrefix=0
+SpiceUseNetNumbers=0
+LabSize=60

MLI/Modular/HBridgePowerModule/HBridgePowerModule.sch

@@ -0,0 +1,196 @@
+EESchema Schematic File Version 2
+LIBS:OAE.Parts
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:HBridgePowerModule-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 5
+Title "MLI HBridge Power Board"
+Date "2017-12-06"
+Rev "Rev 3"
+Comp "Enertechnos Ltd"
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 "For approval by Mansour"
+$EndDescr
+Text GLabel 1850 2350 0    60   Input ~ 0
+DRV_GATE_2
+Text GLabel 1850 2550 0    60   UnSpc ~ 0
+GND_ISO_2
+$Comp
+L RJ45 J1
+U 1 1 59AED755
+P 2300 2200
+F 0 "J1" H 2500 2700 50  0000 C CNN
+F 1 "RJ45" H 2150 2700 50  0000 C CNN
+F 2 "PartsLibraries:RJ45" H 2300 2200 50  0001 C CNN
+F 3 "" H 2300 2200 50  0001 C CNN
+	1    2300 2200
+	0    1    1    0   
+$EndComp
+Text GLabel 1850 2450 0    60   Input ~ 0
+DRV_GATE_1
+Text GLabel 1850 2250 0    60   UnSpc ~ 0
+GND_ISO_1
+Text GLabel 1850 2050 0    60   Input ~ 0
+DRV_GATE_3
+Text GLabel 1850 1850 0    60   UnSpc ~ 0
+GND_ISO_3
+Text GLabel 1850 1950 0    60   Input ~ 0
+DRV_GATE_4
+Text GLabel 1850 2150 0    60   UnSpc ~ 0
+GND_ISO_4
+$Sheet
+S 3550 1150 1400 1300
+U 59AEDD49
+F0 "SinglePowerSwitch 1" 60
+F1 "SinglePowerSwitch.sch" 60
+F2 "DRV_GATE" I L 3550 1400 60 
+F3 "GND_ISO" I L 3550 1500 60 
+F4 "SOURCE" I R 4950 1600 60 
+F5 "DRAIN" I R 4950 2000 60 
+$EndSheet
+Text GLabel 3550 1400 0    60   Input ~ 0
+DRV_GATE_1
+Text GLabel 3550 1500 0    60   Input ~ 0
+GND_ISO_1
+$Sheet
+S 5750 1150 1400 1300
+U 59AEEDCB
+F0 "SinglePowerSwitch 2" 60
+F1 "SinglePowerSwitch.sch" 60
+F2 "DRV_GATE" I R 7150 2200 60 
+F3 "GND_ISO" I R 7150 2100 60 
+F4 "SOURCE" I L 5750 1600 60 
+F5 "DRAIN" I L 5750 2000 60 
+$EndSheet
+Text GLabel 7150 2200 2    60   Input ~ 0
+DRV_GATE_2
+Text GLabel 7150 2100 2    60   Input ~ 0
+GND_ISO_2
+$Sheet
+S 3550 2650 1400 1300
+U 59AEEFC6
+F0 "SinglePowerSwitch 3" 60
+F1 "SinglePowerSwitch.sch" 60
+F2 "DRV_GATE" I L 3550 2900 60 
+F3 "GND_ISO" I L 3550 3000 60 
+F4 "SOURCE" I R 4950 3050 60 
+F5 "DRAIN" I R 4950 3400 60 
+$EndSheet
+Text GLabel 3550 2900 0    60   Input ~ 0
+DRV_GATE_3
+Text GLabel 3550 3000 0    60   Input ~ 0
+GND_ISO_3
+$Sheet
+S 5750 2650 1400 1300
+U 59AEEFCD
+F0 "SinglePowerSwitch 4" 60
+F1 "SinglePowerSwitch.sch" 60
+F2 "DRV_GATE" I R 7150 3700 60 
+F3 "GND_ISO" I R 7150 3600 60 
+F4 "SOURCE" I L 5750 3050 60 
+F5 "DRAIN" I L 5750 3400 60 
+$EndSheet
+Text GLabel 7150 3700 2    60   Input ~ 0
+DRV_GATE_4
+Text GLabel 7150 3600 2    60   Input ~ 0
+GND_ISO_4
+$Comp
+L Conn_01x01 J6
+U 1 1 59AEFF90
+P 5250 2850
+F 0 "J6" H 5250 2950 50  0000 C CNN
+F 1 "AC_OUT" V 5350 2850 50  0000 C CNN
+F 2 "PartsLibraries:PowerConnectorRound" H 5250 2850 50  0001 C CNN
+F 3 "" H 5250 2850 50  0001 C CNN
+	1    5250 2850
+	1    0    0    -1  
+$EndComp
+$Comp
+L Conn_01x01 J7
+U 1 1 59AFA697
+P 5450 2350
+F 0 "J7" H 5450 2450 50  0000 C CNN
+F 1 "AC_OUT" V 5550 2350 50  0000 C CNN
+F 2 "PartsLibraries:PowerConnectorRound" H 5450 2350 50  0001 C CNN
+F 3 "" H 5450 2350 50  0001 C CNN
+	1    5450 2350
+	-1   0    0    1   
+$EndComp
+$Comp
+L Conn_01x01 J2
+U 1 1 5A28227C
+P 5300 1150
+F 0 "J2" H 5300 1250 50  0000 C CNN
+F 1 "POS_IN" V 5400 1150 50  0000 C CNN
+F 2 "PartsLibraries:PowerConnectorRound" H 5300 1150 50  0001 C CNN
+F 3 "" H 5300 1150 50  0001 C CNN
+	1    5300 1150
+	0    -1   -1   0   
+$EndComp
+$Comp
+L Conn_01x01 J3
+U 1 1 5A28246C
+P 5350 3900
+F 0 "J3" H 5350 4000 50  0000 C CNN
+F 1 "NEG_IN" V 5450 3900 50  0000 C CNN
+F 2 "PartsLibraries:PowerConnectorRound" H 5350 3900 50  0001 C CNN
+F 3 "" H 5350 3900 50  0001 C CNN
+	1    5350 3900
+	0    1    1    0   
+$EndComp
+Wire Wire Line
+	4950 1600 5750 1600
+Wire Wire Line
+	5300 1350 5300 1600
+Connection ~ 5300 1600
+Wire Wire Line
+	4950 2000 5050 2000
+Wire Wire Line
+	5050 2000 5050 3050
+Wire Wire Line
+	5050 3050 4950 3050
+Wire Wire Line
+	5750 2000 5650 2000
+Wire Wire Line
+	5650 2000 5650 3050
+Wire Wire Line
+	5650 3050 5750 3050
+Wire Wire Line
+	4950 3400 5750 3400
+Wire Wire Line
+	5350 3700 5350 3400
+Connection ~ 5350 3400
+$EndSCHEMATC

MLI/Modular/HBridgePowerModule/SinglePowerSwitch.sch

@@ -0,0 +1,103 @@
+EESchema Schematic File Version 2
+LIBS:OAE.Parts
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:HBridgePowerModule-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 2 5
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L RFP12N10L Q1
+U 1 1 59AEE014
+P 3650 2100
+AR Path="/59AEDD49/59AEE014" Ref="Q1"  Part="1" 
+AR Path="/59AEEDCB/59AEE014" Ref="Q2"  Part="1" 
+AR Path="/59AEEFC6/59AEE014" Ref="Q3"  Part="1" 
+AR Path="/59AEEFCD/59AEE014" Ref="Q4"  Part="1" 
+F 0 "Q4" H 4200 2250 50  0000 C CNN
+F 1 "RFP12N10L" H 4200 1850 50  0000 C CNN
+F 2 "TO_SOT_Packages_THT:TO-247_TO-3P_Vertical" H 4200 1750 50  0001 C CNN
+F 3 "https://componentsearchengine.com/Datasheets/2/RFP12N10L.pdf" H 4200 1650 50  0001 C CNN
+F 4 "N-channel logicFET,RFP12N10L 12A 100V" H 4200 1550 50  0001 C CNN "Description"
+F 5 "Fairchild Semiconductor" H 4200 1450 50  0001 C CNN "Manufacturer_Name"
+F 6 "RFP12N10L" H 4200 1350 50  0001 C CNN "Manufacturer_Part_Number"
+F 7 "RS" H 4200 1250 50  0001 C CNN "Supplier_Name"
+F 8 "0295703" H 4200 1150 50  0001 C CNN "RS Part Number"
+F 9 "4.7" H 4200 1050 50  0001 C CNN "Height"
+	1    3650 2100
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	4750 2100 5000 2100
+$Comp
+L C C1
+U 1 1 59AEE01D
+P 4450 2550
+AR Path="/59AEDD49/59AEE01D" Ref="C1"  Part="1" 
+AR Path="/59AEEDCB/59AEE01D" Ref="C2"  Part="1" 
+AR Path="/59AEEFC6/59AEE01D" Ref="C3"  Part="1" 
+AR Path="/59AEEFCD/59AEE01D" Ref="C4"  Part="1" 
+F 0 "C4" H 4475 2650 50  0000 L CNN
+F 1 "C" H 4475 2450 50  0000 L CNN
+F 2 "PartsLibraries:CP_Radial_D5.0mm_P2.50mm" H 4488 2400 50  0001 C CNN
+F 3 "" H 4450 2550 50  0001 C CNN
+	1    4450 2550
+	0    1    1    0   
+$EndComp
+Wire Wire Line
+	4600 2550 4850 2550
+Connection ~ 4850 2100
+Connection ~ 4850 2550
+Wire Wire Line
+	4850 2550 4850 2100
+Text HLabel 3650 2100 0    60   Input ~ 0
+DRV_GATE
+Text HLabel 4850 2550 3    60   Input ~ 0
+GND_ISO
+Text HLabel 5000 2100 2    60   Input ~ 0
+SOURCE
+Text HLabel 3650 2550 3    60   Input ~ 0
+DRAIN
+Wire Wire Line
+	3650 2200 3650 2550
+Wire Wire Line
+	3650 2550 4300 2550
+$EndSCHEMATC

MLI/Modular/PsuPowerModule/PsuPowerModule.kicad_pcb

@@ -2,10 +2,10 @@
 
   (general
     (links 29)
-    (no_connects 4)
+    (no_connects 0)
     (area 27.889999 20.269999 221.030001 160.070001)
     (thickness 1.6)
-    (drawings 25)
+    (drawings 59)
     (tracks 81)
     (zones 0)
     (modules 23)
@@ -14,8 +14,8 @@
 
   (page A4)
   (layers
-    (0 F.Cu mixed)
-    (31 B.Cu power)
+    (0 F.Cu mixed hide)
+    (31 B.Cu power hide)
     (32 B.Adhes user hide)
     (33 F.Adhes user hide)
     (34 B.Paste user hide)
@@ -172,12 +172,12 @@
     )
   )
 
-  (module Mounting_Holes:MountingHole_4.3mm_M4 (layer F.Cu) (tedit 56D1B4CB) (tstamp 5A172C6E)
+  (module Mounting_Holes:MountingHole_4.3mm_M4 (layer F.Cu) (tedit 5A27F7A2) (tstamp 5A172C6E)
     (at 182.88 127)
     (descr "Mounting Hole 4.3mm, no annular, M4")
     (tags "mounting hole 4.3mm no annular m4")
     (attr virtual)
-    (fp_text reference REF** (at 0 -5.3) (layer F.SilkS)
+    (fp_text reference "" (at 0 -5.3) (layer F.SilkS)
       (effects (font (size 1 1) (thickness 0.15)))
     )
     (fp_text value MountingHole_4.3mm_M4 (at 0 5.3) (layer F.Fab)
@@ -191,12 +191,12 @@
     (pad 1 np_thru_hole circle (at 0 0) (size 4.3 4.3) (drill 4.3) (layers *.Cu *.Mask))
   )
 
-  (module Mounting_Holes:MountingHole_4.3mm_M4 (layer F.Cu) (tedit 56D1B4CB) (tstamp 5A172C67)
+  (module Mounting_Holes:MountingHole_4.3mm_M4 (layer F.Cu) (tedit 5A27F79F) (tstamp 5A172C67)
     (at 67.31 128.27)
     (descr "Mounting Hole 4.3mm, no annular, M4")
     (tags "mounting hole 4.3mm no annular m4")
     (attr virtual)
-    (fp_text reference REF** (at 0 -5.3) (layer F.SilkS)
+    (fp_text reference "" (at 0 -5.3) (layer F.SilkS)
       (effects (font (size 1 1) (thickness 0.15)))
     )
     (fp_text value MountingHole_4.3mm_M4 (at 0 5.3) (layer F.Fab)
@@ -210,12 +210,12 @@
     (pad 1 np_thru_hole circle (at 0 0) (size 4.3 4.3) (drill 4.3) (layers *.Cu *.Mask))
   )
 
-  (module Mounting_Holes:MountingHole_4.3mm_M4 (layer F.Cu) (tedit 56D1B4CB) (tstamp 5A172C60)
+  (module Mounting_Holes:MountingHole_4.3mm_M4 (layer F.Cu) (tedit 5A27F798) (tstamp 5A172C60)
     (at 182.88 58.42)
     (descr "Mounting Hole 4.3mm, no annular, M4")
     (tags "mounting hole 4.3mm no annular m4")
     (attr virtual)
-    (fp_text reference REF** (at 0 -5.3) (layer F.SilkS)
+    (fp_text reference "" (at 0 -5.3) (layer F.SilkS)
       (effects (font (size 1 1) (thickness 0.15)))
     )
     (fp_text value MountingHole_4.3mm_M4 (at 0 5.3) (layer F.Fab)
@@ -1251,12 +1251,12 @@
       (net 9 "/SinglePowerSwitch 1/PWR_OUT"))
   )
 
-  (module Mounting_Holes:MountingHole_4.3mm_M4 (layer F.Cu) (tedit 56D1B4CB) (tstamp 5A172C5D)
+  (module Mounting_Holes:MountingHole_4.3mm_M4 (layer F.Cu) (tedit 5A27F78E) (tstamp 5A172C5D)
     (at 67.31 59.69)
     (descr "Mounting Hole 4.3mm, no annular, M4")
     (tags "mounting hole 4.3mm no annular m4")
     (attr virtual)
-    (fp_text reference REF** (at 0 -5.3) (layer F.SilkS)
+    (fp_text reference "" (at 0 -5.3) (layer F.SilkS)
       (effects (font (size 1 1) (thickness 0.15)))
     )
     (fp_text value MountingHole_4.3mm_M4 (at 0 5.3) (layer F.Fab)
@@ -1270,6 +1270,40 @@
     (pad 1 np_thru_hole circle (at 0 0) (size 4.3 4.3) (drill 4.3) (layers *.Cu *.Mask))
   )
 
+  (gr_line (start 93.98 88.79) (end 94.09 88.9) (layer F.Mask) (width 5))
+  (gr_line (start 76.2 142.24) (end 76.2 134.99) (layer F.Mask) (width 5))
+  (gr_line (start 76.2 90.17) (end 93.98 90.17) (layer F.Mask) (width 10))
+  (gr_line (start 154.94 142.24) (end 154.94 134.99) (layer F.Mask) (width 5))
+  (gr_line (start 154.94 90.17) (end 172.72 90.17) (layer F.Mask) (width 10))
+  (gr_line (start 93.98 90.17) (end 154.94 90.17) (layer F.Mask) (width 10))
+  (gr_line (start 213.36 90.17) (end 172.72 90.17) (layer F.Mask) (width 10))
+  (gr_line (start 35.56 90.17) (end 76.2 90.17) (layer F.Mask) (width 10))
+  (gr_line (start 172.72 90.17) (end 172.72 45.72) (layer F.Mask) (width 10))
+  (gr_line (start 172.72 38.1) (end 172.72 45.72) (layer F.Mask) (width 5))
+  (gr_line (start 93.98 88.79) (end 93.98 45.72) (layer F.Mask) (width 10))
+  (gr_line (start 93.98 38.1) (end 93.98 45.72) (layer F.Mask) (width 5))
+  (gr_line (start 76.2 90.17) (end 76.2 134.99) (layer F.Mask) (width 10))
+  (gr_line (start 154.94 90.17) (end 154.94 134.99) (layer F.Mask) (width 10))
+  (gr_line (start 172.72 152.4) (end 172.72 149.890001) (layer F.Mask) (width 10))
+  (gr_line (start 172.72 142.24) (end 172.72 149.890001) (layer F.Mask) (width 5))
+  (gr_line (start 164.465 142.24) (end 162.84001 142.24) (layer F.Mask) (width 10))
+  (gr_line (start 160.39 142.24) (end 164.465 142.24) (layer F.Mask) (width 5))
+  (gr_line (start 164.465 142.24) (end 167.27 142.24) (layer F.Mask) (width 5))
+  (gr_line (start 154.94 27.94) (end 154.94 30.449999) (layer F.Mask) (width 10))
+  (gr_line (start 154.94 38.1) (end 154.94 30.449999) (layer F.Mask) (width 5))
+  (gr_line (start 164.81999 38.1) (end 167.27 38.1) (layer F.Mask) (width 5))
+  (gr_line (start 163.195 38.1) (end 164.81999 38.1) (layer F.Mask) (width 10))
+  (gr_line (start 160.39 38.1) (end 163.195 38.1) (layer F.Mask) (width 5))
+  (gr_line (start 93.98 152.4) (end 93.98 149.890001) (layer F.Mask) (width 10))
+  (gr_line (start 93.98 142.24) (end 93.98 149.890001) (layer F.Mask) (width 5))
+  (gr_line (start 84.455 142.24) (end 86.07999 142.24) (layer F.Mask) (width 10))
+  (gr_line (start 81.65 142.24) (end 84.455 142.24) (layer F.Mask) (width 5))
+  (gr_line (start 84.455 142.24) (end 88.53 142.24) (layer F.Mask) (width 5))
+  (gr_line (start 76.2 27.94) (end 76.2 30.449999) (layer F.Mask) (width 10))
+  (gr_line (start 76.2 38.1) (end 76.2 30.449999) (layer F.Mask) (width 5))
+  (gr_line (start 84.455 38.1) (end 86.07999 38.1) (layer F.Mask) (width 10))
+  (gr_line (start 81.65 38.1) (end 84.455 38.1) (layer F.Mask) (width 5))
+  (gr_line (start 84.455 38.1) (end 88.53 38.1) (layer F.Mask) (width 5))
   (dimension 68.58 (width 0.3) (layer Dwgs.User) (tstamp 5A172D78)
     (gr_text "68.580 mm" (at 76.28 93.98 270) (layer Dwgs.User) (tstamp 5A172D79)
       (effects (font (size 1.5 1.5) (thickness 0.3)))
@@ -1439,49 +1473,49 @@
   (gr_line (start 220.98 20.32) (end 220.98 157.48) (layer Edge.Cuts) (width 0.1))
   (gr_line (start 27.94 20.32) (end 215.9 20.32) (layer Edge.Cuts) (width 0.1))
 
+  (segment (start 84.455 38.1) (end 88.53 38.1) (width 5) (layer F.Cu) (net 1))
+  (segment (start 81.65 38.1) (end 84.455 38.1) (width 5) (layer F.Cu) (net 1))
+  (segment (start 84.455 38.1) (end 86.07999 38.1) (width 10) (layer F.Cu) (net 1))
   (segment (start 80.5 45.72) (end 78.7 45.72) (width 1) (layer B.Cu) (net 1))
   (segment (start 107.660574 33.909999) (end 95.850573 45.72) (width 1) (layer B.Cu) (net 1))
   (segment (start 121.539999 33.909999) (end 107.660574 33.909999) (width 1) (layer B.Cu) (net 1))
   (segment (start 95.850573 45.72) (end 80.5 45.72) (width 1) (layer B.Cu) (net 1))
   (segment (start 123.19 35.56) (end 121.539999 33.909999) (width 1) (layer B.Cu) (net 1))
   (segment (start 88.53 37.1) (end 88.53 38.1) (width 1) (layer B.Cu) (net 1))
-  (segment (start 84.455 38.1) (end 88.53 38.1) (width 5) (layer F.Cu) (net 1))
-  (segment (start 81.65 38.1) (end 84.455 38.1) (width 5) (layer F.Cu) (net 1))
-  (segment (start 84.455 38.1) (end 86.07999 38.1) (width 10) (layer F.Cu) (net 1))
   (segment (start 81.65 38.1) (end 81.65 42.77) (width 1) (layer B.Cu) (net 1))
   (segment (start 81.65 42.77) (end 78.7 45.72) (width 1) (layer B.Cu) (net 1))
   (segment (start 78.74 45.76) (end 78.7 45.72) (width 1) (layer B.Cu) (net 1))
   (segment (start 76.2 38.1) (end 76.2 30.449999) (width 5) (layer F.Cu) (net 2))
   (segment (start 76.2 27.94) (end 76.2 30.449999) (width 10) (layer F.Cu) (net 2))
   (segment (start 76.2 45.72) (end 76.2 38.1) (width 1) (layer B.Cu) (net 2))
-  (segment (start 91.48 134.62) (end 91.48 66) (width 1) (layer B.Cu) (net 3))
-  (segment (start 91.48 66) (end 119.38 38.1) (width 1) (layer B.Cu) (net 3))
   (segment (start 84.455 142.24) (end 88.53 142.24) (width 5) (layer F.Cu) (net 3))
   (segment (start 81.65 142.24) (end 84.455 142.24) (width 5) (layer F.Cu) (net 3))
   (segment (start 84.455 142.24) (end 86.07999 142.24) (width 10) (layer F.Cu) (net 3))
+  (segment (start 91.48 134.62) (end 91.48 66) (width 1) (layer B.Cu) (net 3))
+  (segment (start 91.48 66) (end 119.38 38.1) (width 1) (layer B.Cu) (net 3))
   (segment (start 88.53 142.24) (end 88.53 135.77) (width 1) (layer B.Cu) (net 3))
   (segment (start 88.53 135.77) (end 89.68 134.62) (width 1) (layer B.Cu) (net 3))
   (segment (start 89.68 134.62) (end 91.48 134.62) (width 1) (layer B.Cu) (net 3))
   (segment (start 93.98 142.24) (end 93.98 149.890001) (width 5) (layer F.Cu) (net 4))
   (segment (start 93.98 152.4) (end 93.98 149.890001) (width 10) (layer F.Cu) (net 4))
   (segment (start 93.98 134.62) (end 93.98 142.24) (width 1) (layer B.Cu) (net 4))
+  (segment (start 160.39 38.1) (end 163.195 38.1) (width 5) (layer F.Cu) (net 5))
+  (segment (start 163.195 38.1) (end 164.81999 38.1) (width 10) (layer F.Cu) (net 5))
+  (segment (start 164.81999 38.1) (end 167.27 38.1) (width 5) (layer F.Cu) (net 5))
   (segment (start 128.27 35.56) (end 130.02 35.56) (width 1) (layer B.Cu) (net 5))
   (segment (start 130.02 35.56) (end 141.880001 47.420001) (width 1) (layer B.Cu) (net 5))
   (segment (start 155.739999 47.420001) (end 157.44 45.72) (width 1) (layer B.Cu) (net 5))
   (segment (start 141.880001 47.420001) (end 155.739999 47.420001) (width 1) (layer B.Cu) (net 5))
-  (segment (start 160.39 38.1) (end 163.195 38.1) (width 5) (layer F.Cu) (net 5))
-  (segment (start 163.195 38.1) (end 164.81999 38.1) (width 10) (layer F.Cu) (net 5))
-  (segment (start 164.81999 38.1) (end 167.27 38.1) (width 5) (layer F.Cu) (net 5))
   (segment (start 160.39 38.1) (end 160.39 42.77) (width 1) (layer B.Cu) (net 5))
   (segment (start 160.39 42.77) (end 157.44 45.72) (width 1) (layer B.Cu) (net 5))
   (segment (start 154.94 38.1) (end 154.94 30.449999) (width 5) (layer F.Cu) (net 6))
   (segment (start 154.94 27.94) (end 154.94 30.449999) (width 10) (layer F.Cu) (net 6))
   (segment (start 154.94 38.1) (end 154.94 45.72) (width 1) (layer B.Cu) (net 6))
-  (segment (start 170.22 134.62) (end 170.22 83.86) (width 1) (layer B.Cu) (net 7))
-  (segment (start 170.22 83.86) (end 124.46 38.1) (width 1) (layer B.Cu) (net 7))
   (segment (start 164.465 142.24) (end 167.27 142.24) (width 5) (layer F.Cu) (net 7))
   (segment (start 160.39 142.24) (end 164.465 142.24) (width 5) (layer F.Cu) (net 7))
   (segment (start 164.465 142.24) (end 162.84001 142.24) (width 10) (layer F.Cu) (net 7))
+  (segment (start 170.22 134.62) (end 170.22 83.86) (width 1) (layer B.Cu) (net 7))
+  (segment (start 170.22 83.86) (end 124.46 38.1) (width 1) (layer B.Cu) (net 7))
   (segment (start 160.39 141.24) (end 160.39 142.24) (width 1) (layer B.Cu) (net 7))
   (segment (start 167.27 142.24) (end 167.27 137.57) (width 1) (layer B.Cu) (net 7))
   (segment (start 167.27 137.57) (end 170.22 134.62) (width 1) (layer B.Cu) (net 7))

MLI/Modular/PsuPowerModule/PsuPowerModule.kicad_pcb-bak

@@ -2,11 +2,11 @@
 
   (general
     (links 29)
-    (no_connects 8)
-    (area 27.889999 20.269999 221.030001 160.070001)
+    (no_connects 0)
+    (area 9.215716 13.81 236.45 160.180001)
     (thickness 1.6)
     (drawings 25)
-    (tracks 71)
+    (tracks 81)
     (zones 0)
     (modules 23)
     (nets 14)
@@ -14,8 +14,8 @@
 
   (page A4)
   (layers
-    (0 F.Cu mixed)
-    (31 B.Cu power)
+    (0 F.Cu mixed hide)
+    (31 B.Cu power hide)
     (32 B.Adhes user hide)
     (33 F.Adhes user hide)
     (34 B.Paste user hide)
@@ -150,21 +150,21 @@
     (pad "" np_thru_hole circle (at 10.16 6.35 180) (size 3.65 3.65) (drill 3.25) (layers *.Cu *.SilkS *.Mask))
     (pad "" np_thru_hole circle (at -1.27 6.35 180) (size 3.65 3.65) (drill 3.25) (layers *.Cu *.SilkS *.Mask))
     (pad 1 thru_hole rect (at 0 0 180) (size 1.5 1.5) (drill 0.9) (layers *.Cu *.Mask)
-      (net 13 DRV_GATE_4))
-    (pad 2 thru_hole circle (at 1.27 -2.54 180) (size 1.5 1.5) (drill 0.9) (layers *.Cu *.Mask)
       (net 5 GND_ISO_3))
+    (pad 2 thru_hole circle (at 1.27 -2.54 180) (size 1.5 1.5) (drill 0.9) (layers *.Cu *.Mask)
+      (net 13 DRV_GATE_4))
     (pad 3 thru_hole circle (at 2.54 0 180) (size 1.5 1.5) (drill 0.9) (layers *.Cu *.Mask)
       (net 12 DRV_GATE_3))
     (pad 4 thru_hole circle (at 3.81 -2.54 180) (size 1.5 1.5) (drill 0.9) (layers *.Cu *.Mask)
       (net 7 GND_ISO_4))
     (pad 5 thru_hole circle (at 5.08 0 180) (size 1.5 1.5) (drill 0.9) (layers *.Cu *.Mask)
-      (net 10 DRV_GATE_1))
+      (net 1 GND_ISO_1))
     (pad 6 thru_hole circle (at 6.35 -2.54 180) (size 1.5 1.5) (drill 0.9) (layers *.Cu *.Mask)
-      (net 3 GND_ISO_2))
-    (pad 7 thru_hole circle (at 7.62 0 180) (size 1.5 1.5) (drill 0.9) (layers *.Cu *.Mask)
       (net 11 DRV_GATE_2))
+    (pad 7 thru_hole circle (at 7.62 0 180) (size 1.5 1.5) (drill 0.9) (layers *.Cu *.Mask)
+      (net 10 DRV_GATE_1))
     (pad 8 thru_hole circle (at 8.89 -2.54 180) (size 1.5 1.5) (drill 0.9) (layers *.Cu *.Mask)
-      (net 1 GND_ISO_1))
+      (net 3 GND_ISO_2))
     (model ../../../../../../Development/multilevelinverter/Hardware/3D/RJ45.wrl
       (at (xyz 0.175 -0.667 0.3))
       (scale (xyz 10 10 10))
@@ -1439,23 +1439,26 @@
   (gr_line (start 220.98 20.32) (end 220.98 157.48) (layer Edge.Cuts) (width 0.1))
   (gr_line (start 27.94 20.32) (end 215.9 20.32) (layer Edge.Cuts) (width 0.1))
 
-  (segment (start 119.38 38.1) (end 111.76 45.72) (width 1) (layer B.Cu) (net 1))
-  (segment (start 111.76 45.72) (end 78.7 45.72) (width 1) (layer B.Cu) (net 1))
-  (segment (start 88.53 37.1) (end 88.53 38.1) (width 1) (layer B.Cu) (net 1))
   (segment (start 84.455 38.1) (end 88.53 38.1) (width 5) (layer F.Cu) (net 1))
   (segment (start 81.65 38.1) (end 84.455 38.1) (width 5) (layer F.Cu) (net 1))
   (segment (start 84.455 38.1) (end 86.07999 38.1) (width 10) (layer F.Cu) (net 1))
+  (segment (start 80.5 45.72) (end 78.7 45.72) (width 1) (layer B.Cu) (net 1))
+  (segment (start 107.660574 33.909999) (end 95.850573 45.72) (width 1) (layer B.Cu) (net 1))
+  (segment (start 121.539999 33.909999) (end 107.660574 33.909999) (width 1) (layer B.Cu) (net 1))
+  (segment (start 95.850573 45.72) (end 80.5 45.72) (width 1) (layer B.Cu) (net 1))
+  (segment (start 123.19 35.56) (end 121.539999 33.909999) (width 1) (layer B.Cu) (net 1))
+  (segment (start 88.53 37.1) (end 88.53 38.1) (width 1) (layer B.Cu) (net 1))
   (segment (start 81.65 38.1) (end 81.65 42.77) (width 1) (layer B.Cu) (net 1))
   (segment (start 81.65 42.77) (end 78.7 45.72) (width 1) (layer B.Cu) (net 1))
   (segment (start 78.74 45.76) (end 78.7 45.72) (width 1) (layer B.Cu) (net 1))
   (segment (start 76.2 38.1) (end 76.2 30.449999) (width 5) (layer F.Cu) (net 2))
   (segment (start 76.2 27.94) (end 76.2 30.449999) (width 10) (layer F.Cu) (net 2))
   (segment (start 76.2 45.72) (end 76.2 38.1) (width 1) (layer B.Cu) (net 2))
-  (segment (start 121.92 38.1) (end 121.92 104.18) (width 1) (layer B.Cu) (net 3))
-  (segment (start 121.92 104.18) (end 91.48 134.62) (width 1) (layer B.Cu) (net 3))
   (segment (start 84.455 142.24) (end 88.53 142.24) (width 5) (layer F.Cu) (net 3))
   (segment (start 81.65 142.24) (end 84.455 142.24) (width 5) (layer F.Cu) (net 3))
   (segment (start 84.455 142.24) (end 86.07999 142.24) (width 10) (layer F.Cu) (net 3))
+  (segment (start 91.48 134.62) (end 91.48 66) (width 1) (layer B.Cu) (net 3))
+  (segment (start 91.48 66) (end 119.38 38.1) (width 1) (layer B.Cu) (net 3))
   (segment (start 88.53 142.24) (end 88.53 135.77) (width 1) (layer B.Cu) (net 3))
   (segment (start 88.53 135.77) (end 89.68 134.62) (width 1) (layer B.Cu) (net 3))
   (segment (start 89.68 134.62) (end 91.48 134.62) (width 1) (layer B.Cu) (net 3))
@@ -1465,16 +1468,20 @@
   (segment (start 160.39 38.1) (end 163.195 38.1) (width 5) (layer F.Cu) (net 5))
   (segment (start 163.195 38.1) (end 164.81999 38.1) (width 10) (layer F.Cu) (net 5))
   (segment (start 164.81999 38.1) (end 167.27 38.1) (width 5) (layer F.Cu) (net 5))
+  (segment (start 128.27 35.56) (end 130.02 35.56) (width 1) (layer B.Cu) (net 5))
+  (segment (start 130.02 35.56) (end 141.880001 47.420001) (width 1) (layer B.Cu) (net 5))
+  (segment (start 155.739999 47.420001) (end 157.44 45.72) (width 1) (layer B.Cu) (net 5))
+  (segment (start 141.880001 47.420001) (end 155.739999 47.420001) (width 1) (layer B.Cu) (net 5))
   (segment (start 160.39 38.1) (end 160.39 42.77) (width 1) (layer B.Cu) (net 5))
   (segment (start 160.39 42.77) (end 157.44 45.72) (width 1) (layer B.Cu) (net 5))
   (segment (start 154.94 38.1) (end 154.94 30.449999) (width 5) (layer F.Cu) (net 6))
   (segment (start 154.94 27.94) (end 154.94 30.449999) (width 10) (layer F.Cu) (net 6))
   (segment (start 154.94 38.1) (end 154.94 45.72) (width 1) (layer B.Cu) (net 6))
-  (segment (start 170.22 134.62) (end 170.22 83.86) (width 1) (layer B.Cu) (net 7))
-  (segment (start 170.22 83.86) (end 124.46 38.1) (width 1) (layer B.Cu) (net 7))
   (segment (start 164.465 142.24) (end 167.27 142.24) (width 5) (layer F.Cu) (net 7))
   (segment (start 160.39 142.24) (end 164.465 142.24) (width 5) (layer F.Cu) (net 7))
   (segment (start 164.465 142.24) (end 162.84001 142.24) (width 10) (layer F.Cu) (net 7))
+  (segment (start 170.22 134.62) (end 170.22 83.86) (width 1) (layer B.Cu) (net 7))
+  (segment (start 170.22 83.86) (end 124.46 38.1) (width 1) (layer B.Cu) (net 7))
   (segment (start 160.39 141.24) (end 160.39 142.24) (width 1) (layer B.Cu) (net 7))
   (segment (start 167.27 142.24) (end 167.27 137.57) (width 1) (layer B.Cu) (net 7))
   (segment (start 167.27 137.57) (end 170.22 134.62) (width 1) (layer B.Cu) (net 7))
@@ -1495,20 +1502,23 @@
   (segment (start 76.2 90.17) (end 93.98 90.17) (width 10) (layer F.Cu) (net 9))
   (segment (start 76.2 142.24) (end 76.2 134.99) (width 5) (layer F.Cu) (net 9))
   (segment (start 93.98 88.79) (end 94.09 88.9) (width 5) (layer F.Cu) (net 9))
-  (segment (start 123.19 35.56) (end 121.539999 33.909999) (width 1) (layer B.Cu) (net 10))
-  (segment (start 121.539999 33.909999) (end 73.940001 33.909999) (width 1) (layer B.Cu) (net 10))
-  (segment (start 73.940001 33.909999) (end 70.75 37.1) (width 1) (layer B.Cu) (net 10))
+  (segment (start 75.383999 47.420001) (end 70.75 42.786002) (width 1) (layer B.Cu) (net 10))
+  (segment (start 120.65 35.56) (end 107.990487 35.56) (width 1) (layer B.Cu) (net 10))
+  (segment (start 107.990487 35.56) (end 96.130486 47.420001) (width 1) (layer B.Cu) (net 10))
+  (segment (start 96.130486 47.420001) (end 75.383999 47.420001) (width 1) (layer B.Cu) (net 10))
+  (segment (start 70.75 42.786002) (end 70.75 41.35) (width 1) (layer B.Cu) (net 10))
+  (segment (start 70.75 41.35) (end 70.75 38.1) (width 1) (layer B.Cu) (net 10))
   (segment (start 70.75 37.1) (end 70.75 38.1) (width 1) (layer B.Cu) (net 10))
+  (segment (start 99.43 142.24) (end 99.43 60.59) (width 1) (layer B.Cu) (net 11))
+  (segment (start 99.43 60.59) (end 121.92 38.1) (width 1) (layer B.Cu) (net 11))
   (segment (start 149.49 38.1) (end 147.24 38.1) (width 1) (layer B.Cu) (net 12))
   (segment (start 147.24 38.1) (end 143.049999 33.909999) (width 1) (layer B.Cu) (net 12))
   (segment (start 143.049999 33.909999) (end 126.319341 33.909999) (width 1) (layer B.Cu) (net 12))
   (segment (start 126.319341 33.909999) (end 125.73 34.49934) (width 1) (layer B.Cu) (net 12))
   (segment (start 125.73 34.49934) (end 125.73 35.56) (width 1) (layer B.Cu) (net 12))
   (segment (start 149.49 39.1) (end 149.49 38.1) (width 1) (layer B.Cu) (net 12))
-  (segment (start 128.27 35.56) (end 130.02 35.56) (width 1) (layer B.Cu) (net 13))
-  (segment (start 130.02 35.56) (end 178.17 83.71) (width 1) (layer B.Cu) (net 13))
-  (segment (start 178.17 83.71) (end 178.17 138.99) (width 1) (layer B.Cu) (net 13))
-  (segment (start 178.17 138.99) (end 178.17 142.24) (width 1) (layer B.Cu) (net 13))
+  (segment (start 178.17 142.24) (end 178.17 89.27) (width 1) (layer B.Cu) (net 13))
+  (segment (start 178.17 89.27) (end 127 38.1) (width 1) (layer B.Cu) (net 13))
   (segment (start 178.17 143.24) (end 178.17 142.24) (width 1) (layer B.Cu) (net 13))
 
 )

MLI/Modular/PsuPowerModule/PsuPowerModule.pro

@@ -1,4 +1,4 @@
-update=24/10/2017 14:51:49
+update=06/12/2017 14:01:49
 version=1
 last_client=kicad
 [pcbnew]
@@ -29,34 +29,43 @@ version=1
 version=1
 LibDir=
 [eeschema/libraries]
-LibName1=PsuPowerModule-rescue
-LibName2=C:/Development/multilevelinverter/Hardware/PartsLibraries/OAE.Parts
-LibName3=power
-LibName4=device
-LibName5=transistors
-LibName6=conn
-LibName7=linear
-LibName8=regul
-LibName9=74xx
-LibName10=cmos4000
-LibName11=adc-dac
-LibName12=memory
-LibName13=xilinx
-LibName14=microcontrollers
-LibName15=dsp
-LibName16=microchip
-LibName17=analog_switches
-LibName18=motorola
-LibName19=texas
-LibName20=intel
-LibName21=audio
-LibName22=interface
-LibName23=digital-audio
-LibName24=philips
-LibName25=display
-LibName26=cypress
-LibName27=siliconi
-LibName28=opto
-LibName29=atmel
-LibName30=contrib
-LibName31=valves
+LibName1=C:/Development/multilevelinverter/Hardware/PartsLibraries/OAE.Parts
+LibName2=power
+LibName3=device
+LibName4=transistors
+LibName5=conn
+LibName6=linear
+LibName7=regul
+LibName8=74xx
+LibName9=cmos4000
+LibName10=adc-dac
+LibName11=memory
+LibName12=xilinx
+LibName13=microcontrollers
+LibName14=dsp
+LibName15=microchip
+LibName16=analog_switches
+LibName17=motorola
+LibName18=texas
+LibName19=intel
+LibName20=audio
+LibName21=interface
+LibName22=digital-audio
+LibName23=philips
+LibName24=display
+LibName25=cypress
+LibName26=siliconi
+LibName27=opto
+LibName28=atmel
+LibName29=contrib
+LibName30=valves
+[schematic_editor]
+version=1
+PageLayoutDescrFile=
+PlotDirectoryName=
+SubpartIdSeparator=0
+SubpartFirstId=65
+NetFmtName=
+SpiceForceRefPrefix=0
+SpiceUseNetNumbers=0
+LabSize=60

MLI/Modular/PsuSwitchModule/PsuSwitchModule.kicad_pcb-bak

@@ -2,14 +2,14 @@
 
   (general
     (links 148)
-    (no_connects 1)
+    (no_connects 0)
     (area 44.852857 29.145205 184.346292 114.525)
     (thickness 1.6)
     (drawings 29)
-    (tracks 482)
+    (tracks 484)
     (zones 0)
     (modules 69)
-    (nets 34)
+    (nets 49)
   )
 
   (page A4)
@@ -35,17 +35,17 @@
     (trace_clearance 0.4)
     (zone_clearance 0.35)
     (zone_45_only no)
-    (trace_min 0.2)
+    (trace_min 1)
     (segment_width 0.2)
     (edge_width 0.15)
     (via_size 1.5)
     (via_drill 1)
-    (via_min_size 0.4)
+    (via_min_size 1.5)
     (via_min_drill 0.3)
     (uvia_size 1)
     (uvia_drill 0.5)
     (uvias_allowed no)
-    (uvia_min_size 0.2)
+    (uvia_min_size 1)
     (uvia_min_drill 0.1)
     (pcb_text_width 0.3)
     (pcb_text_size 1.5 1.5)
@@ -118,6 +118,21 @@
   (net 31 GND_ISO_B)
   (net 32 GND_ISO_C)
   (net 33 GND_ISO_D)
+  (net 34 "Net-(IC1-Pad3)")
+  (net 35 "Net-(IC2-Pad3)")
+  (net 36 "Net-(IC3-Pad3)")
+  (net 37 "Net-(IC4-Pad3)")
+  (net 38 "Net-(J1-Pad1)")
+  (net 39 "Net-(J1-Pad2)")
+  (net 40 "Net-(J1-Pad3)")
+  (net 41 "Net-(J1-Pad4)")
+  (net 42 "Net-(J1-Pad5)")
+  (net 43 "Net-(J7-Pad7)")
+  (net 44 "Net-(J7-Pad8)")
+  (net 45 "Net-(U2-Pad3)")
+  (net 46 "Net-(U4-Pad3)")
+  (net 47 "Net-(U6-Pad3)")
+  (net 48 "Net-(U8-Pad3)")
 
   (net_class Default "This is the default net class."
     (clearance 0.4)
@@ -156,9 +171,24 @@
     (add_net "Net-(C27-Pad1)")
     (add_net "Net-(C28-Pad1)")
     (add_net "Net-(IC1-Pad2)")
+    (add_net "Net-(IC1-Pad3)")
     (add_net "Net-(IC2-Pad2)")
+    (add_net "Net-(IC2-Pad3)")
     (add_net "Net-(IC3-Pad2)")
+    (add_net "Net-(IC3-Pad3)")
     (add_net "Net-(IC4-Pad2)")
+    (add_net "Net-(IC4-Pad3)")
+    (add_net "Net-(J1-Pad1)")
+    (add_net "Net-(J1-Pad2)")
+    (add_net "Net-(J1-Pad3)")
+    (add_net "Net-(J1-Pad4)")
+    (add_net "Net-(J1-Pad5)")
+    (add_net "Net-(J7-Pad7)")
+    (add_net "Net-(J7-Pad8)")
+    (add_net "Net-(U2-Pad3)")
+    (add_net "Net-(U4-Pad3)")
+    (add_net "Net-(U6-Pad3)")
+    (add_net "Net-(U8-Pad3)")
   )
 
   (module PartsLibraries:RJ45 (layer F.Cu) (tedit 5A16E9AB) (tstamp 59A7E8CF)
@@ -195,8 +225,10 @@
       (net 19 ARD_PWM_C))
     (pad 6 thru_hole circle (at 6.35 -2.54 90) (size 1.5 1.5) (drill 0.9) (layers *.Cu *.Mask)
       (net 20 ARD_PWM_D))
-    (pad 7 thru_hole circle (at 7.62 0 90) (size 1.5 1.5) (drill 0.9) (layers *.Cu *.Mask))
-    (pad 8 thru_hole circle (at 8.89 -2.54 90) (size 1.5 1.5) (drill 0.9) (layers *.Cu *.Mask))
+    (pad 7 thru_hole circle (at 7.62 0 90) (size 1.5 1.5) (drill 0.9) (layers *.Cu *.Mask)
+      (net 43 "Net-(J7-Pad7)"))
+    (pad 8 thru_hole circle (at 8.89 -2.54 90) (size 1.5 1.5) (drill 0.9) (layers *.Cu *.Mask)
+      (net 44 "Net-(J7-Pad8)"))
     (model ../../../../../../Development/multilevelinverter/Hardware/3D/RJ45.wrl
       (at (xyz 0.175 -0.667 0.3))
       (scale (xyz 10 10 10))
@@ -226,11 +258,16 @@
     (fp_line (start 12.46 14.47) (end -3.56 14.47) (layer F.CrtYd) (width 0.05))
     (pad "" np_thru_hole circle (at 10.16 6.35 90) (size 3.65 3.65) (drill 3.25) (layers *.Cu *.SilkS *.Mask))
     (pad "" np_thru_hole circle (at -1.27 6.35 90) (size 3.65 3.65) (drill 3.25) (layers *.Cu *.SilkS *.Mask))
-    (pad 1 thru_hole rect (at 0 0 90) (size 1.5 1.5) (drill 0.9) (layers *.Cu *.Mask))
-    (pad 2 thru_hole circle (at 1.27 -2.54 90) (size 1.5 1.5) (drill 0.9) (layers *.Cu *.Mask))
-    (pad 3 thru_hole circle (at 2.54 0 90) (size 1.5 1.5) (drill 0.9) (layers *.Cu *.Mask))
-    (pad 4 thru_hole circle (at 3.81 -2.54 90) (size 1.5 1.5) (drill 0.9) (layers *.Cu *.Mask))
-    (pad 5 thru_hole circle (at 5.08 0 90) (size 1.5 1.5) (drill 0.9) (layers *.Cu *.Mask))
+    (pad 1 thru_hole rect (at 0 0 90) (size 1.5 1.5) (drill 0.9) (layers *.Cu *.Mask)
+      (net 38 "Net-(J1-Pad1)"))
+    (pad 2 thru_hole circle (at 1.27 -2.54 90) (size 1.5 1.5) (drill 0.9) (layers *.Cu *.Mask)
+      (net 39 "Net-(J1-Pad2)"))
+    (pad 3 thru_hole circle (at 2.54 0 90) (size 1.5 1.5) (drill 0.9) (layers *.Cu *.Mask)
+      (net 40 "Net-(J1-Pad3)"))
+    (pad 4 thru_hole circle (at 3.81 -2.54 90) (size 1.5 1.5) (drill 0.9) (layers *.Cu *.Mask)
+      (net 41 "Net-(J1-Pad4)"))
+    (pad 5 thru_hole circle (at 5.08 0 90) (size 1.5 1.5) (drill 0.9) (layers *.Cu *.Mask)
+      (net 42 "Net-(J1-Pad5)"))
     (pad 6 thru_hole circle (at 6.35 -2.54 90) (size 1.5 1.5) (drill 0.9) (layers *.Cu *.Mask)
       (net 10 ARD_TEMP))
     (pad 7 thru_hole circle (at 7.62 0 90) (size 1.5 1.5) (drill 0.9) (layers *.Cu *.Mask)
@@ -363,7 +400,8 @@
       (net 11 ARD_GND))
     (pad 5 thru_hole oval (at 7.62 2.54) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
       (net 32 GND_ISO_C))
-    (pad 3 thru_hole oval (at 0 5.08) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
+    (pad 3 thru_hole oval (at 0 5.08) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 47 "Net-(U6-Pad3)"))
     (pad 6 thru_hole oval (at 7.62 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
       (net 15 "Net-(C21-Pad1)"))
     (model ${KISYS3DMOD}/Housings_DIP.3dshapes/DIP-6_W7.62mm.wrl
@@ -448,7 +486,8 @@
       (net 11 ARD_GND))
     (pad 5 thru_hole oval (at 7.62 2.54) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
       (net 33 GND_ISO_D))
-    (pad 3 thru_hole oval (at 0 5.08) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
+    (pad 3 thru_hole oval (at 0 5.08) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 48 "Net-(U8-Pad3)"))
     (pad 6 thru_hole oval (at 7.62 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
       (net 16 "Net-(C23-Pad1)"))
     (model ${KISYS3DMOD}/Housings_DIP.3dshapes/DIP-6_W7.62mm.wrl
@@ -817,7 +856,8 @@
       (net 16 "Net-(C23-Pad1)"))
     (pad 2 thru_hole circle (at 0 2.54 90) (size 1.4859 1.4859) (drill 0.9906) (layers *.Cu *.Mask F.SilkS)
       (net 7 "Net-(IC4-Pad2)"))
-    (pad 3 thru_hole circle (at 0 5.08 90) (size 1.4859 1.4859) (drill 0.9906) (layers *.Cu *.Mask F.SilkS))
+    (pad 3 thru_hole circle (at 0 5.08 90) (size 1.4859 1.4859) (drill 0.9906) (layers *.Cu *.Mask F.SilkS)
+      (net 37 "Net-(IC4-Pad3)"))
     (pad 4 thru_hole circle (at 0 7.62 90) (size 1.4859 1.4859) (drill 0.9906) (layers *.Cu *.Mask F.SilkS)
       (net 33 GND_ISO_D))
     (pad 5 thru_hole circle (at 7.62 7.62 90) (size 1.4859 1.4859) (drill 0.9906) (layers *.Cu *.Mask F.SilkS)
@@ -893,7 +933,8 @@
       (net 14 "Net-(C19-Pad1)"))
     (pad 2 thru_hole circle (at 0 2.54 90) (size 1.4859 1.4859) (drill 0.9906) (layers *.Cu *.Mask F.SilkS)
       (net 5 "Net-(IC2-Pad2)"))
-    (pad 3 thru_hole circle (at 0 5.08 90) (size 1.4859 1.4859) (drill 0.9906) (layers *.Cu *.Mask F.SilkS))
+    (pad 3 thru_hole circle (at 0 5.08 90) (size 1.4859 1.4859) (drill 0.9906) (layers *.Cu *.Mask F.SilkS)
+      (net 35 "Net-(IC2-Pad3)"))
     (pad 4 thru_hole circle (at 0 7.62 90) (size 1.4859 1.4859) (drill 0.9906) (layers *.Cu *.Mask F.SilkS)
       (net 31 GND_ISO_B))
     (pad 5 thru_hole circle (at 7.62 7.62 90) (size 1.4859 1.4859) (drill 0.9906) (layers *.Cu *.Mask F.SilkS)
@@ -969,7 +1010,8 @@
       (net 15 "Net-(C21-Pad1)"))
     (pad 2 thru_hole circle (at 0 2.54 90) (size 1.4859 1.4859) (drill 0.9906) (layers *.Cu *.Mask F.SilkS)
       (net 6 "Net-(IC3-Pad2)"))
-    (pad 3 thru_hole circle (at 0 5.08 90) (size 1.4859 1.4859) (drill 0.9906) (layers *.Cu *.Mask F.SilkS))
+    (pad 3 thru_hole circle (at 0 5.08 90) (size 1.4859 1.4859) (drill 0.9906) (layers *.Cu *.Mask F.SilkS)
+      (net 36 "Net-(IC3-Pad3)"))
     (pad 4 thru_hole circle (at 0 7.62 90) (size 1.4859 1.4859) (drill 0.9906) (layers *.Cu *.Mask F.SilkS)
       (net 32 GND_ISO_C))
     (pad 5 thru_hole circle (at 7.62 7.62 90) (size 1.4859 1.4859) (drill 0.9906) (layers *.Cu *.Mask F.SilkS)
@@ -1045,7 +1087,8 @@
       (net 13 "Net-(C17-Pad1)"))
     (pad 2 thru_hole circle (at 0 2.54 90) (size 1.4859 1.4859) (drill 0.9906) (layers *.Cu *.Mask F.SilkS)
       (net 4 "Net-(IC1-Pad2)"))
-    (pad 3 thru_hole circle (at 0 5.08 90) (size 1.4859 1.4859) (drill 0.9906) (layers *.Cu *.Mask F.SilkS))
+    (pad 3 thru_hole circle (at 0 5.08 90) (size 1.4859 1.4859) (drill 0.9906) (layers *.Cu *.Mask F.SilkS)
+      (net 34 "Net-(IC1-Pad3)"))
     (pad 4 thru_hole circle (at 0 7.62 90) (size 1.4859 1.4859) (drill 0.9906) (layers *.Cu *.Mask F.SilkS)
       (net 22 GND_ISO_A))
     (pad 5 thru_hole circle (at 7.62 7.62 90) (size 1.4859 1.4859) (drill 0.9906) (layers *.Cu *.Mask F.SilkS)
@@ -3391,7 +3434,8 @@
       (net 11 ARD_GND))
     (pad 5 thru_hole oval (at 7.62 2.54) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
       (net 22 GND_ISO_A))
-    (pad 3 thru_hole oval (at 0 5.08) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
+    (pad 3 thru_hole oval (at 0 5.08) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 45 "Net-(U2-Pad3)"))
     (pad 6 thru_hole oval (at 7.62 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
       (net 13 "Net-(C17-Pad1)"))
     (model ${KISYS3DMOD}/Housings_DIP.3dshapes/DIP-6_W7.62mm.wrl
@@ -3438,7 +3482,8 @@
       (net 11 ARD_GND))
     (pad 5 thru_hole oval (at 7.62 2.54) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
       (net 31 GND_ISO_B))
-    (pad 3 thru_hole oval (at 0 5.08) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
+    (pad 3 thru_hole oval (at 0 5.08) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 46 "Net-(U4-Pad3)"))
     (pad 6 thru_hole oval (at 7.62 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
       (net 14 "Net-(C19-Pad1)"))
     (model ${KISYS3DMOD}/Housings_DIP.3dshapes/DIP-6_W7.62mm.wrl
@@ -4076,6 +4121,8 @@
   (segment (start 136.787049 57.522951) (end 136.787049 58.792951) (width 1) (layer F.Cu) (net 6))
   (segment (start 136.787049 58.792951) (end 134.657999 60.922001) (width 1) (layer F.Cu) (net 6))
   (segment (start 134.657999 60.922001) (end 133.858 61.722) (width 1) (layer F.Cu) (net 6))
+  (segment (start 134.62 99.06) (end 139.446 103.886) (width 1) (layer F.Cu) (net 7))
+  (segment (start 139.446 103.886) (end 139.446 105.41) (width 1) (layer F.Cu) (net 7))
   (segment (start 138.43 93.98) (end 136.787049 95.622951) (width 1) (layer F.Cu) (net 7))
   (segment (start 136.787049 95.622951) (end 136.787049 96.892951) (width 1) (layer F.Cu) (net 7))
   (segment (start 136.787049 96.892951) (end 135.419999 98.260001) (width 1) (layer F.Cu) (net 7))

MLI/Modular/PsuSwitchModule/PsuSwitchModule.net

@@ -1,8 +1,8 @@
 (export (version D)
   (design
     (source C:/Development/MliHardware/MLI/Modular/PsuSwitchModule/PsuSwitchModule.sch)
-    (date "06/12/2017 11:33:53")
-    (tool "Eeschema 4.0.6")
+    (date "06/12/2017 14:06:27")
+    (tool "Eeschema 4.0.7")
     (sheet (number 1) (name /) (tstamps /)
       (title_block
         (title "Power Module (Control Board)")
@@ -68,7 +68,7 @@
     (comp (ref J2)
       (value "Temperature Probe")
       (footprint Connectors_JST:JST_XH_B02B-XH-A_02x2.50mm_Straight)
-      (libsource (lib PsuSwitchModule-cache) (part Conn_01x02))
+      (libsource (lib conn) (part Conn_01x02))
       (sheetpath (names /) (tstamps /))
       (tstamp 599EAAF2))
     (comp (ref R1)
@@ -494,7 +494,9 @@
       (pins
         (pin (num 1) (name ~) (type passive))
         (pin (num 2) (name ~) (type passive))))
-    (libpart (lib PsuSwitchModule-cache) (part Conn_01x02)
+    (libpart (lib conn) (part Conn_01x02)
+      (description "Generic connector, single row, 01x02")
+      (docs ~)
       (footprints
         (fp Connector*:*_??x*mm*)
         (fp Connector*:*1x??x*mm*)
@@ -595,6 +597,8 @@
       (uri C:\Development\multilevelinverter\Hardware\PartsLibraries\OAE.Parts.lib))
     (library (logical device)
       (uri "C:\\Program Files\\KiCad\\share\\kicad\\library\\device.lib"))
+    (library (logical conn)
+      (uri "C:\\Program Files\\KiCad\\share\\kicad\\library\\conn.lib"))
     (library (logical PsuSwitchModule-cache)
       (uri C:\Development\MliHardware\MLI\Modular\PsuSwitchModule\PsuSwitchModule-cache.lib)))
   (nets
@@ -627,7 +631,7 @@
       (node (ref U1) (pin 4))
       (node (ref U5) (pin 4))
       (node (ref U7) (pin 4)))
-    (net (code 8) (name GND_ISO_C)
+    (net (code 8) (name GND_ISO_3)
       (node (ref C12) (pin 2))
       (node (ref R15) (pin 2))
       (node (ref IC3) (pin 5))
@@ -641,7 +645,7 @@
       (node (ref C11) (pin 1))
       (node (ref C10) (pin 2))
       (node (ref C22) (pin 2)))
-    (net (code 9) (name GND_ISO_B)
+    (net (code 9) (name GND_ISO_2)
       (node (ref C5) (pin 2))
       (node (ref C7) (pin 1))
       (node (ref C19) (pin 2))
@@ -655,14 +659,14 @@
       (node (ref IC2) (pin 4))
       (node (ref IC2) (pin 5))
       (node (ref D2) (pin 2)))
-    (net (code 10) (name DRV_SIG_A)
+    (net (code 10) (name DRV_GATE_A)
       (node (ref J3) (pin 7))
       (node (ref C3) (pin 2))
       (node (ref IC1) (pin 7))
       (node (ref C4) (pin 1))
       (node (ref IC1) (pin 6))
       (node (ref R11) (pin 1)))
-    (net (code 11) (name GND_ISO_A)
+    (net (code 11) (name GND_ISO_1)
       (node (ref C17) (pin 2))
       (node (ref C2) (pin 2))
       (node (ref C1) (pin 2))
@@ -676,7 +680,7 @@
       (node (ref U1) (pin 7))
       (node (ref C18) (pin 2))
       (node (ref D1) (pin 2)))
-    (net (code 12) (name GND_ISO_D)
+    (net (code 12) (name GND_ISO_4)
       (node (ref IC4) (pin 5))
       (node (ref U7) (pin 7))
       (node (ref IC4) (pin 4))
@@ -690,14 +694,14 @@
       (node (ref C23) (pin 2))
       (node (ref R17) (pin 2))
       (node (ref D4) (pin 2)))
-    (net (code 13) (name DRV_SIG_C)
+    (net (code 13) (name DRV_GATE_C)
       (node (ref C11) (pin 2))
       (node (ref C12) (pin 1))
       (node (ref IC3) (pin 7))
       (node (ref J3) (pin 3))
       (node (ref IC3) (pin 6))
       (node (ref R15) (pin 1)))
-    (net (code 14) (name DRV_SIG_D)
+    (net (code 14) (name DRV_GATE_D)
       (node (ref C16) (pin 1))
       (node (ref C15) (pin 2))
       (node (ref J3) (pin 2))
@@ -731,7 +735,7 @@
       (node (ref C28) (pin 2))
       (node (ref J7) (pin 6))
       (node (ref R8) (pin 1)))
-    (net (code 24) (name DRV_SIG_B)
+    (net (code 24) (name DRV_GATE_B)
       (node (ref R13) (pin 1))
       (node (ref IC2) (pin 7))
       (node (ref J3) (pin 6))

MLI/Modular/PsuSwitchModule/PsuSwitchModule.pro

@@ -1,4 +1,4 @@
-update=23/11/2017 16:24:42
+update=06/12/2017 14:03:11
 version=1
 last_client=kicad
 [pcbnew]
@@ -25,41 +25,6 @@ version=1
 NetIExt=net
 [general]
 version=1
-[eeschema]
-version=1
-LibDir=
-[eeschema/libraries]
-LibName1=PsuSwitchModule-rescue
-LibName2=C:/Development/multilevelinverter/Hardware/PartsLibraries/OAE.Parts
-LibName3=power
-LibName4=device
-LibName5=transistors
-LibName6=conn
-LibName7=linear
-LibName8=regul
-LibName9=74xx
-LibName10=cmos4000
-LibName11=adc-dac
-LibName12=memory
-LibName13=xilinx
-LibName14=microcontrollers
-LibName15=dsp
-LibName16=microchip
-LibName17=analog_switches
-LibName18=motorola
-LibName19=texas
-LibName20=intel
-LibName21=audio
-LibName22=interface
-LibName23=digital-audio
-LibName24=philips
-LibName25=display
-LibName26=cypress
-LibName27=siliconi
-LibName28=opto
-LibName29=atmel
-LibName30=contrib
-LibName31=valves
 [schematic_editor]
 version=1
 PageLayoutDescrFile=
@@ -70,3 +35,37 @@ NetFmtName=Pcbnew
 SpiceForceRefPrefix=0
 SpiceUseNetNumbers=0
 LabSize=60
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=C:/Development/multilevelinverter/Hardware/PartsLibraries/OAE.Parts
+LibName2=power
+LibName3=device
+LibName4=transistors
+LibName5=conn
+LibName6=linear
+LibName7=regul
+LibName8=74xx
+LibName9=cmos4000
+LibName10=adc-dac
+LibName11=memory
+LibName12=xilinx
+LibName13=microcontrollers
+LibName14=dsp
+LibName15=microchip
+LibName16=analog_switches
+LibName17=motorola
+LibName18=texas
+LibName19=intel
+LibName20=audio
+LibName21=interface
+LibName22=digital-audio
+LibName23=philips
+LibName24=display
+LibName25=cypress
+LibName26=siliconi
+LibName27=opto
+LibName28=atmel
+LibName29=contrib
+LibName30=valves

MLI/Modular/PsuSwitchModule/PsuSwitchModule.sch

@@ -214,37 +214,37 @@ F 3 "" H 10150 3150 50  0001 C CNN
 	0    1    1    0   
 $EndComp
 Text GLabel 5800 2300 2    60   Output ~ 0
-DRV_SIG_A
+DRV_GATE_A
 Text GLabel 5800 2600 2    60   UnSpc ~ 0
-GND_ISO_A
+GND_ISO_1
 Text GLabel 8100 2250 2    60   Output ~ 0
-DRV_SIG_C
+DRV_GATE_C
 Text GLabel 8100 2550 2    60   UnSpc ~ 0
-GND_ISO_C
+GND_ISO_3
 Text GLabel 5800 3800 2    60   Output ~ 0
-DRV_SIG_B
+DRV_GATE_B
 Text GLabel 5800 4100 2    60   UnSpc ~ 0
-GND_ISO_B
+GND_ISO_2
 Text GLabel 8100 3800 2    60   Output ~ 0
-DRV_SIG_D
+DRV_GATE_D
 Text GLabel 8100 4100 2    60   UnSpc ~ 0
-GND_ISO_D
+GND_ISO_4
 Text GLabel 9700 3400 0    60   Input ~ 0
-DRV_SIG_A
+DRV_GATE_A
 Text GLabel 9700 3200 0    60   UnSpc ~ 0
-GND_ISO_A
+GND_ISO_1
 Text GLabel 9700 3300 0    60   Input ~ 0
-DRV_SIG_B
+DRV_GATE_B
 Text GLabel 9700 3500 0    60   UnSpc ~ 0
-GND_ISO_B
+GND_ISO_2
 Text GLabel 9700 3000 0    60   Input ~ 0
-DRV_SIG_C
+DRV_GATE_C
 Text GLabel 9700 2800 0    60   UnSpc ~ 0
-GND_ISO_C
+GND_ISO_3
 Text GLabel 9700 2900 0    60   Input ~ 0
-DRV_SIG_D
+DRV_GATE_D
 Text GLabel 9700 3100 0    60   UnSpc ~ 0
-GND_ISO_D
+GND_ISO_4
 Text Notes 1250 1550 0    60   ~ 0
 In the event there are 2 arduinos on the control board \n(one for driving, the other for monitoring) the runs for \neach should be kept on separate RJ45s for clarity.
 $EndSCHEMATC