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Rev 4.2 Ready for review

Gareth 4 anos atrás
pai
commit
68ccd33dba

+ 4 - 4
MLI/Modular/PsuSwitchModule/PsuSwitchModule.Switch.sch

@@ -5,12 +5,12 @@ $Descr User 8268 5846
 encoding utf-8
 Sheet 2 5
 Title "Power Module (Control Board)"
-Date "2020-02-19"
-Rev "Release 4.1a"
+Date "2020-11-24"
+Rev "Release 4.2"
 Comp "Enertechnos Ltd"
 Comment1 "FOR APPROVAL"
-Comment2 ""
-Comment3 ""
+Comment2 "Extra Capicitor Removed"
+Comment3 "Ground planes connected to Earth instead of DC_GND"
 Comment4 ""
 $EndDescr
 $Comp

+ 4 - 4
MLI/Modular/PsuSwitchModule/PsuSwitchModule.Switch.sch-bak

@@ -1,6 +1,5 @@
 EESchema Schematic File Version 4
-LIBS:PsuSwitchModule-cache
-EELAYER 29 0
+EELAYER 30 0
 EELAYER END
 $Descr User 8268 5846
 encoding utf-8
@@ -66,13 +65,14 @@ F 3 "" H 2100 2800 50  0001 C CNN
 	0    -1   -1   0   
 $EndComp
 $Comp
-L OAE.Parts:H11N1M U2
+L PsuSwitchModule-rescue:H11N1M-OAE.Parts U2
 U 1 1 59A6DAA6
 P 2550 2900
 AR Path="/59498AA5/59A6DAA6" Ref="U2"  Part="1" 
 AR Path="/59A7109E/59A6DAA6" Ref="U4"  Part="1" 
 AR Path="/59A71299/59A6DAA6" Ref="U6"  Part="1" 
 AR Path="/59A712A3/59A6DAA6" Ref="U8"  Part="1" 
+AR Path="/59A6DAA6" Ref="U2"  Part="1" 
 F 0 "U2" H 2350 3100 50  0000 L CNN
 F 1 "H11N1M" H 2550 2700 50  0000 C CNN
 F 2 "Housings_DIP:DIP-6_W7.62mm" H 2350 2700 50  0001 L CIN
@@ -292,7 +292,7 @@ Text HLabel 2950 1450 2    60   Input ~ 0
 Text Label 3050 1250 0    60   ~ 0
 +15V
 $Comp
-L OAE.Parts:NMA1215DC U201
+L PsuSwitchModule-rescue:NMA1215DC-OAE.Parts U201
 U 1 1 5E39E16E
 P 2500 1400
 AR Path="/59498AA5/5E39E16E" Ref="U201"  Part="1" 

+ 986 - 0
MLI/Modular/PsuSwitchModule/PsuSwitchModule.dsn

@@ -0,0 +1,986 @@
+(pcb C:\development\MliHardware\2020\MLI\Modular\PsuSwitchModule\PsuSwitchModule.dsn
+  (parser
+    (string_quote ")
+    (space_in_quoted_tokens on)
+    (host_cad "KiCad's Pcbnew")
+    (host_version "(5.1.6)-1")
+  )
+  (resolution um 10)
+  (unit um)
+  (structure
+    (layer F.Cu
+      (type signal)
+      (property
+        (index 0)
+      )
+    )
+    (layer B.Cu
+      (type signal)
+      (property
+        (index 1)
+      )
+    )
+    (boundary
+      (path pcb 0  175260 -113030  49530 -113030  49530 -34290  175260 -34290
+            175260 -113030)
+    )
+    (plane Earth (polygon F.Cu 0  50546 -33020  175514 -33274  175260 -114554  50292 -114554
+            50292 -33020  50546 -33020))
+    (plane Earth (polygon B.Cu 0  50038 -33020  175514 -33274  175514 -114554  50800 -114554
+            50038 -33528  50038 -33274  50038 -33020))
+    (via "Via[0-1]_1500:1000_um")
+    (rule
+      (width 1000)
+      (clearance 400.1)
+      (clearance 400.1 (type default_smd))
+      (clearance 100 (type smd_smd))
+    )
+  )
+  (placement
+    (component Capacitors_THT:CP_Radial_Tantal_D4.5mm_P2.50mm
+      (place C2 88265 -54610 front 0 (PN 100nF))
+      (place C10 156210 -54960 front 0 (PN 100nF))
+      (place C18 94655 -54610 front 0 (PN 100nF))
+      (place C17 94655 -62230 front 0 (PN 100nF))
+      (place C3 81955 -62230 front 0 (PN C))
+      (place C27 133390 -69850 front 0 (PN 100nF))
+      (place C28 133310 -107950 front 180 (PN 100nF))
+      (place C23 163830 -90170 front 0 (PN 100nF))
+      (place C24 163830 -83820 front 0 (PN 100nF))
+      (place C14 157520 -83820 front 0 (PN 100nF))
+      (place C15 151170 -90170 front 0 (PN C))
+      (place C6 88700 -84316.4 front 0 (PN 100nF))
+      (place C7 82590 -90805 front 0 (PN C))
+      (place C11 149860 -62230 front 0 (PN C))
+      (place C19 95290 -90805 front 0 (PN 100nF))
+      (place C20 95010 -84316.4 front 0 (PN 100nF))
+      (place C21 162560 -62230 front 0 (PN 100nF))
+      (place C22 162560 -54960 front 0 (PN 100nF))
+      (place C25 58420 -66040 front 270 (PN 100nF))
+      (place C26 60325 -107950 front 0 (PN 100nF))
+    )
+    (component Capacitors_THT:CP_Radial_D5.0mm_P2.50mm
+      (place C1 81955 -54610 front 0 (PN 4.7uF))
+      (place C13 151170 -83820 front 0 (PN 4.7uF))
+      (place C5 82350 -84316.4 front 0 (PN 4.7uF))
+      (place C9 149900 -54960 front 0 (PN 4.7uF))
+    )
+    (component Resistors_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P7.62mm_Horizontal
+      (place R201 71120 -50165 front 0 (PN R))
+      (place R3 58420 -53848 front 0 (PN 3K))
+      (place R204 89662 -50038 front 180 (PN R))
+      (place R203 92710 -50165 front 0 (PN R))
+      (place R2 71120 -67310 front 180 (PN 180))
+      (place R10 83439 -67310 front 180 (PN R))
+      (place R11 88265 -67310 front 0 (PN R))
+      (place R504 146050 -78105 front 270 (PN R))
+      (place R503 147320 -107950 front 180 (PN R))
+      (place R404 170815 -43180 front 270 (PN R))
+      (place R403 149225 -50165 front 0 (PN R))
+      (place R304 97790 -78740 front 180 (PN R))
+      (place R303 98425 -108585 front 90 (PN R))
+      (place R16 147320 -104140 front 180 (PN R))
+      (place R17 157480 -95250 front 0 (PN R))
+      (place R12 74930 -105410 front 180 (PN R))
+      (place R8 128270 -102870 front 0 (PN 180))
+      (place R9 163195 -79375 front 0 (PN 3K))
+      (place R1 119380 -74930 front 90 (PN 100))
+      (place R4 64135 -102870 front 180 (PN 180))
+      (place R13 92710 -95885 front 0 (PN R))
+      (place R14 146050 -64770 front 180 (PN R))
+      (place R15 151765 -67310 front 0 (PN R))
+      (place R5 55245 -90170 front 0 (PN 3K))
+      (place R7 160020 -50165 front 0 (PN 3K))
+      (place R6 134620 -64770 front 180 (PN 180))
+      (place R302 73025 -90170 front 180 (PN R))
+      (place R401 128270 -49530 front 0 (PN R))
+      (place R501 127000 -88900 front 0 (PN R))
+    )
+    (component "Diodes_THT:D_A-405_P7.62mm_Horizontal"
+      (place D202 58420 -50292 front 0 (PN DIODE))
+      (place D502 139065 -88900 front 0 (PN DIODE))
+      (place D402 163195 -67310 front 0 (PN DIODE))
+      (place D302 79375 -78740 front 0 (PN DIODE))
+    )
+    (component Resistors_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P7.62mm_Horizontal::1
+      (place R202 78740 -45720 front 90 (PN R))
+      (place R301 81280 -95885 front 0 (PN R))
+      (place R402 138430 -49530 front 0 (PN R))
+      (place R502 152654 -78994 front 0 (PN R))
+    )
+    (component "Housings_DIP:DIP-14_W7.62mm_Socket"
+      (place U201 59055 -46355 front 90 (PN NMA1215DC))
+      (place U501 127000 -85090 front 90 (PN NMA1215DC))
+    )
+    (component "OAE_Parts:SOT-23_HandSoldering"
+      (place D201 83185 -41910 front 0 (PN D_Zener_x2_KCom_AKA))
+      (place D301 76835 -83820 front 90 (PN D_Zener_x2_KCom_AKA))
+      (place D401 146050 -39370 front 0 (PN D_Zener_x2_KCom_AKA))
+      (place D501 170180 -97790 front 0 (PN D_Zener_x2_KCom_AKA))
+    )
+    (component "OAE_Parts:TerminalBlock_Altech_AK300-3_P5.00mm"
+      (place J201 88900 -41275 front 0 (PN Conn_01x03_Male))
+      (place J501 163750 -104140 front 180 (PN Conn_01x03_Male))
+      (place J301 92075 -104775 front 180 (PN Conn_01x03_Male))
+      (place J401 152400 -41910 front 0 (PN Conn_01x03_Male))
+    )
+    (component PartsLibraries:MountingHole_M3
+      (place MountTL 54610 -38100 front 0 (PN Mount))
+      (place MountBR 170180 -107950 front 0 (PN Mount))
+      (place MountTR 170180 -38100 front 0 (PN Mount))
+      (place MountBL 54610 -107950 front 0 (PN Mount))
+    )
+    (component "Diodes_THT:D_T-1_P5.08mm_Horizontal"
+      (place D1 100965 -59690 front 90 (PN D_Zener))
+      (place D4 170180 -90170 front 90 (PN D_Zener))
+      (place D2 101600 -90805 front 90 (PN D_Zener))
+      (place D3 168910 -59690 front 90 (PN D_Zener))
+    )
+    (component OAE_Parts:TC4422AVPA
+      (place IC1 70485 -53340 front 0 (PN TC4421CPA))
+      (place IC3 138430 -53340 front 0 (PN TC4421CPA))
+      (place IC2 67310 -93980 front 0 (PN TC4421CPA))
+      (place IC4 139700 -92710 front 0 (PN TC4421CPA))
+    )
+    (component "Housings_DIP:DIP-6_W7.62mm"
+      (place U2 58293 -57150 front 0 (PN H11N1M))
+      (place U8 128270 -93980 front 0 (PN H11N1M))
+      (place U6 126365 -54610 front 0 (PN H11N1M))
+      (place U4 55118 -94488 front 0 (PN H11N1M))
+    )
+    (component "Connectors_JST:JST_XH_B03B-XH-A_03x2.50mm_Straight"
+      (place J2 109220 -77470 front 0 (PN "Temperature Probe LM35"))
+      (place J101 114300 -69850 front 180 (PN "Current Sensor"))
+    )
+    (component "Housings_DIP:DIP-14_W7.62mm_Socket::1"
+      (place U301 56515 -86360 front 90 (PN NMA1215DC))
+      (place U401 125730 -45720 front 90 (PN NMA1215DC))
+    )
+    (component OAE_Parts:PowerConnectorRound_M3
+      (place J102 116840 -109220 front 0 (PN Earth))
+    )
+    (component "OAE_Parts:RJ45-shielded-Molex"
+      (place J1 117655 -97790 front 180 (PN Monitor))
+      (place J7 116840 -57150 front 180 (PN Control))
+    )
+  )
+  (library
+    (image Capacitors_THT:CP_Radial_Tantal_D4.5mm_P2.50mm
+      (outline (path signal 100  3500 0  3423.33 -582.343  3198.56 -1125  2840.99 -1590.99
+            2375 -1948.56  1832.34 -2173.33  1250 -2250  667.657 -2173.33
+            125 -1948.56  -340.99 -1590.99  -698.557 -1125  -923.333 -582.343
+            -1000 0  -923.333 582.343  -698.557 1125  -340.99 1590.99  125 1948.56
+            667.657 2173.33  1250 2250  1832.34 2173.33  2375 1948.56  2840.99 1590.99
+            3198.56 1125  3423.33 582.343  3500 0))
+      (outline (path signal 100  -2200 0  -1000 0))
+      (outline (path signal 100  -1600 650  -1600 -650))
+      (outline (path signal 120  -2200 0  -1000 0))
+      (outline (path signal 120  -1600 650  -1600 -650))
+      (outline (path signal 50  -1350 2600  -1350 -2600))
+      (outline (path signal 50  -1350 -2600  3850 -2600))
+      (outline (path signal 50  3850 -2600  3850 2600))
+      (outline (path signal 50  3850 2600  -1350 2600))
+      (pin Rect[A]Pad_1600x1600_um 1 0 0)
+      (pin Round[A]Pad_1600_um 2 2500 0)
+    )
+    (image Capacitors_THT:CP_Radial_D5.0mm_P2.50mm
+      (outline (path signal 100  3750 0  3671.46 -621.725  3440.77 -1204.38  3072.42 -1711.37
+            2589.57 -2110.82  2022.54 -2377.64  1406.98 -2495.07  781.547 -2455.72
+            185.552 -2262.07  -343.56 -1926.28  -772.542 -1469.46  -1074.44 -920.311
+            -1230.29 -313.333  -1230.29 313.333  -1074.44 920.311  -772.542 1469.46
+            -343.56 1926.28  185.552 2262.07  781.547 2455.72  1406.98 2495.07
+            2022.54 2377.64  2589.57 2110.82  3072.42 1711.37  3440.77 1204.38
+            3671.46 621.725  3750 0))
+      (outline (path signal 100  -2200 0  -1000 0))
+      (outline (path signal 100  -1600 650  -1600 -650))
+      (outline (path signal 120  1250 2550  1250 -2550))
+      (outline (path signal 120  1290 2550  1290 -2550))
+      (outline (path signal 120  1330 2549  1330 -2549))
+      (outline (path signal 120  1370 2548  1370 -2548))
+      (outline (path signal 120  1410 2546  1410 -2546))
+      (outline (path signal 120  1450 2543  1450 -2543))
+      (outline (path signal 120  1490 2539  1490 -2539))
+      (outline (path signal 120  1530 2535  1530 980))
+      (outline (path signal 120  1530 -980  1530 -2535))
+      (outline (path signal 120  1570 2531  1570 980))
+      (outline (path signal 120  1570 -980  1570 -2531))
+      (outline (path signal 120  1610 2525  1610 980))
+      (outline (path signal 120  1610 -980  1610 -2525))
+      (outline (path signal 120  1650 2519  1650 980))
+      (outline (path signal 120  1650 -980  1650 -2519))
+      (outline (path signal 120  1690 2513  1690 980))
+      (outline (path signal 120  1690 -980  1690 -2513))
+      (outline (path signal 120  1730 2506  1730 980))
+      (outline (path signal 120  1730 -980  1730 -2506))
+      (outline (path signal 120  1770 2498  1770 980))
+      (outline (path signal 120  1770 -980  1770 -2498))
+      (outline (path signal 120  1810 2489  1810 980))
+      (outline (path signal 120  1810 -980  1810 -2489))
+      (outline (path signal 120  1850 2480  1850 980))
+      (outline (path signal 120  1850 -980  1850 -2480))
+      (outline (path signal 120  1890 2470  1890 980))
+      (outline (path signal 120  1890 -980  1890 -2470))
+      (outline (path signal 120  1930 2460  1930 980))
+      (outline (path signal 120  1930 -980  1930 -2460))
+      (outline (path signal 120  1971 2448  1971 980))
+      (outline (path signal 120  1971 -980  1971 -2448))
+      (outline (path signal 120  2011 2436  2011 980))
+      (outline (path signal 120  2011 -980  2011 -2436))
+      (outline (path signal 120  2051 2424  2051 980))
+      (outline (path signal 120  2051 -980  2051 -2424))
+      (outline (path signal 120  2091 2410  2091 980))
+      (outline (path signal 120  2091 -980  2091 -2410))
+      (outline (path signal 120  2131 2396  2131 980))
+      (outline (path signal 120  2131 -980  2131 -2396))
+      (outline (path signal 120  2171 2382  2171 980))
+      (outline (path signal 120  2171 -980  2171 -2382))
+      (outline (path signal 120  2211 2366  2211 980))
+      (outline (path signal 120  2211 -980  2211 -2366))
+      (outline (path signal 120  2251 2350  2251 980))
+      (outline (path signal 120  2251 -980  2251 -2350))
+      (outline (path signal 120  2291 2333  2291 980))
+      (outline (path signal 120  2291 -980  2291 -2333))
+      (outline (path signal 120  2331 2315  2331 980))
+      (outline (path signal 120  2331 -980  2331 -2315))
+      (outline (path signal 120  2371 2296  2371 980))
+      (outline (path signal 120  2371 -980  2371 -2296))
+      (outline (path signal 120  2411 2276  2411 980))
+      (outline (path signal 120  2411 -980  2411 -2276))
+      (outline (path signal 120  2451 2256  2451 980))
+      (outline (path signal 120  2451 -980  2451 -2256))
+      (outline (path signal 120  2491 2234  2491 980))
+      (outline (path signal 120  2491 -980  2491 -2234))
+      (outline (path signal 120  2531 2212  2531 980))
+      (outline (path signal 120  2531 -980  2531 -2212))
+      (outline (path signal 120  2571 2189  2571 980))
+      (outline (path signal 120  2571 -980  2571 -2189))
+      (outline (path signal 120  2611 2165  2611 980))
+      (outline (path signal 120  2611 -980  2611 -2165))
+      (outline (path signal 120  2651 2140  2651 980))
+      (outline (path signal 120  2651 -980  2651 -2140))
+      (outline (path signal 120  2691 2113  2691 980))
+      (outline (path signal 120  2691 -980  2691 -2113))
+      (outline (path signal 120  2731 2086  2731 980))
+      (outline (path signal 120  2731 -980  2731 -2086))
+      (outline (path signal 120  2771 2058  2771 980))
+      (outline (path signal 120  2771 -980  2771 -2058))
+      (outline (path signal 120  2811 2028  2811 980))
+      (outline (path signal 120  2811 -980  2811 -2028))
+      (outline (path signal 120  2851 1997  2851 980))
+      (outline (path signal 120  2851 -980  2851 -1997))
+      (outline (path signal 120  2891 1965  2891 980))
+      (outline (path signal 120  2891 -980  2891 -1965))
+      (outline (path signal 120  2931 1932  2931 980))
+      (outline (path signal 120  2931 -980  2931 -1932))
+      (outline (path signal 120  2971 1897  2971 980))
+      (outline (path signal 120  2971 -980  2971 -1897))
+      (outline (path signal 120  3011 1861  3011 980))
+      (outline (path signal 120  3011 -980  3011 -1861))
+      (outline (path signal 120  3051 1823  3051 980))
+      (outline (path signal 120  3051 -980  3051 -1823))
+      (outline (path signal 120  3091 1783  3091 980))
+      (outline (path signal 120  3091 -980  3091 -1783))
+      (outline (path signal 120  3131 1742  3131 980))
+      (outline (path signal 120  3131 -980  3131 -1742))
+      (outline (path signal 120  3171 1699  3171 980))
+      (outline (path signal 120  3171 -980  3171 -1699))
+      (outline (path signal 120  3211 1654  3211 980))
+      (outline (path signal 120  3211 -980  3211 -1654))
+      (outline (path signal 120  3251 1606  3251 980))
+      (outline (path signal 120  3251 -980  3251 -1606))
+      (outline (path signal 120  3291 1556  3291 980))
+      (outline (path signal 120  3291 -980  3291 -1556))
+      (outline (path signal 120  3331 1504  3331 980))
+      (outline (path signal 120  3331 -980  3331 -1504))
+      (outline (path signal 120  3371 1448  3371 980))
+      (outline (path signal 120  3371 -980  3371 -1448))
+      (outline (path signal 120  3411 1390  3411 980))
+      (outline (path signal 120  3411 -980  3411 -1390))
+      (outline (path signal 120  3451 1327  3451 980))
+      (outline (path signal 120  3451 -980  3451 -1327))
+      (outline (path signal 120  3491 1261  3491 -1261))
+      (outline (path signal 120  3531 1189  3531 -1189))
+      (outline (path signal 120  3571 1112  3571 -1112))
+      (outline (path signal 120  3611 1028  3611 -1028))
+      (outline (path signal 120  3651 934  3651 -934))
+      (outline (path signal 120  3691 829  3691 -829))
+      (outline (path signal 120  3731 707  3731 -707))
+      (outline (path signal 120  3771 559  3771 -559))
+      (outline (path signal 120  3811 354  3811 -354))
+      (outline (path signal 120  -2200 0  -1000 0))
+      (outline (path signal 120  -1600 650  -1600 -650))
+      (outline (path signal 50  -1600 2850  -1600 -2850))
+      (outline (path signal 50  -1600 -2850  4100 -2850))
+      (outline (path signal 50  4100 -2850  4100 2850))
+      (outline (path signal 50  4100 2850  -1600 2850))
+      (pin Rect[A]Pad_1600x1600_um 1 0 0)
+      (pin Round[A]Pad_1600_um 2 2500 0)
+    )
+    (image Resistors_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P7.62mm_Horizontal
+      (outline (path signal 100  660 1250  660 -1250))
+      (outline (path signal 100  660 -1250  6960 -1250))
+      (outline (path signal 100  6960 -1250  6960 1250))
+      (outline (path signal 100  6960 1250  660 1250))
+      (outline (path signal 100  0 0  660 0))
+      (outline (path signal 100  7620 0  6960 0))
+      (outline (path signal 120  600 980  600 1310))
+      (outline (path signal 120  600 1310  7020 1310))
+      (outline (path signal 120  7020 1310  7020 980))
+      (outline (path signal 120  600 -980  600 -1310))
+      (outline (path signal 120  600 -1310  7020 -1310))
+      (outline (path signal 120  7020 -1310  7020 -980))
+      (outline (path signal 50  -1050 1600  -1050 -1600))
+      (outline (path signal 50  -1050 -1600  8700 -1600))
+      (outline (path signal 50  8700 -1600  8700 1600))
+      (outline (path signal 50  8700 1600  -1050 1600))
+      (pin Round[A]Pad_1600_um 1 0 0)
+      (pin Oval[A]Pad_1600x1600_um 2 7620 0)
+    )
+    (image "Diodes_THT:D_A-405_P7.62mm_Horizontal"
+      (outline (path signal 100  1210 1350  1210 -1350))
+      (outline (path signal 100  1210 -1350  6410 -1350))
+      (outline (path signal 100  6410 -1350  6410 1350))
+      (outline (path signal 100  6410 1350  1210 1350))
+      (outline (path signal 100  0 0  1210 0))
+      (outline (path signal 100  7620 0  6410 0))
+      (outline (path signal 100  1990 1350  1990 -1350))
+      (outline (path signal 120  1150 1410  1150 -1410))
+      (outline (path signal 120  1150 -1410  6470 -1410))
+      (outline (path signal 120  6470 -1410  6470 1410))
+      (outline (path signal 120  6470 1410  1150 1410))
+      (outline (path signal 120  1080 0  1150 0))
+      (outline (path signal 120  6540 0  6470 0))
+      (outline (path signal 120  1990 1410  1990 -1410))
+      (outline (path signal 50  -1150 1700  -1150 -1700))
+      (outline (path signal 50  -1150 -1700  8800 -1700))
+      (outline (path signal 50  8800 -1700  8800 1700))
+      (outline (path signal 50  8800 1700  -1150 1700))
+      (pin Rect[A]Pad_1800x1800_um 1 0 0)
+      (pin Oval[A]Pad_1800x1800_um 2 7620 0)
+    )
+    (image Resistors_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P7.62mm_Horizontal::1
+      (outline (path signal 50  8700 1600  -1050 1600))
+      (outline (path signal 50  8700 -1600  8700 1600))
+      (outline (path signal 50  -1050 -1600  8700 -1600))
+      (outline (path signal 50  -1050 1600  -1050 -1600))
+      (outline (path signal 120  7020 -1310  7020 -980))
+      (outline (path signal 120  600 -1310  7020 -1310))
+      (outline (path signal 120  600 -980  600 -1310))
+      (outline (path signal 120  7020 1310  7020 980))
+      (outline (path signal 120  600 1310  7020 1310))
+      (outline (path signal 120  600 980  600 1310))
+      (outline (path signal 100  7620 0  6960 0))
+      (outline (path signal 100  0 0  660 0))
+      (outline (path signal 100  6960 1250  660 1250))
+      (outline (path signal 100  6960 -1250  6960 1250))
+      (outline (path signal 100  660 -1250  6960 -1250))
+      (outline (path signal 100  660 1250  660 -1250))
+      (pin Oval[A]Pad_1600x1600_um 2 7620 0)
+      (pin Round[A]Pad_1600_um 1 0 0)
+    )
+    (image "Housings_DIP:DIP-14_W7.62mm_Socket"
+      (outline (path signal 100  1635 1270  6985 1270))
+      (outline (path signal 100  6985 1270  6985 -16510))
+      (outline (path signal 100  6985 -16510  635 -16510))
+      (outline (path signal 100  635 -16510  635 270))
+      (outline (path signal 100  635 270  1635 1270))
+      (outline (path signal 100  -1270 1330  -1270 -16570))
+      (outline (path signal 100  -1270 -16570  8890 -16570))
+      (outline (path signal 100  8890 -16570  8890 1330))
+      (outline (path signal 100  8890 1330  -1270 1330))
+      (outline (path signal 120  2810 1330  1160 1330))
+      (outline (path signal 120  1160 1330  1160 -16570))
+      (outline (path signal 120  1160 -16570  6460 -16570))
+      (outline (path signal 120  6460 -16570  6460 1330))
+      (outline (path signal 120  6460 1330  4810 1330))
+      (outline (path signal 120  -1330 1390  -1330 -16630))
+      (outline (path signal 120  -1330 -16630  8950 -16630))
+      (outline (path signal 120  8950 -16630  8950 1390))
+      (outline (path signal 120  8950 1390  -1330 1390))
+      (outline (path signal 50  -1550 1600  -1550 -16850))
+      (outline (path signal 50  -1550 -16850  9150 -16850))
+      (outline (path signal 50  9150 -16850  9150 1600))
+      (outline (path signal 50  9150 1600  -1550 1600))
+      (pin Rect[A]Pad_1600x1600_um 1 0 0)
+      (pin Oval[A]Pad_1600x1600_um 8 7620 -15240)
+      (pin Oval[A]Pad_1600x1600_um 2 0 -2540)
+      (pin Oval[A]Pad_1600x1600_um 9 7620 -12700)
+      (pin Oval[A]Pad_1600x1600_um 3 0 -5080)
+      (pin Oval[A]Pad_1600x1600_um 10 7620 -10160)
+      (pin Oval[A]Pad_1600x1600_um 4 0 -7620)
+      (pin Oval[A]Pad_1600x1600_um 11 7620 -7620)
+      (pin Oval[A]Pad_1600x1600_um 5 0 -10160)
+      (pin Oval[A]Pad_1600x1600_um 12 7620 -5080)
+      (pin Oval[A]Pad_1600x1600_um 6 0 -12700)
+      (pin Oval[A]Pad_1600x1600_um 13 7620 -2540)
+      (pin Oval[A]Pad_1600x1600_um 7 0 -15240)
+      (pin Oval[A]Pad_1600x1600_um 14 7620 0)
+    )
+    (image "OAE_Parts:SOT-23_HandSoldering"
+      (outline (path signal 120  760 -1580  -700 -1580))
+      (outline (path signal 120  760 1580  -1400 1580))
+      (outline (path signal 50  -1700 -1750  -1700 1750))
+      (outline (path signal 50  1700 -1750  -1700 -1750))
+      (outline (path signal 50  1700 1750  1700 -1750))
+      (outline (path signal 50  -1700 1750  1700 1750))
+      (outline (path signal 120  760 1580  760 650))
+      (outline (path signal 120  760 -1580  760 -650))
+      (outline (path signal 100  -700 -1520  700 -1520))
+      (outline (path signal 100  700 1520  700 -1520))
+      (outline (path signal 100  -700 950  -150 1520))
+      (outline (path signal 100  -150 1520  700 1520))
+      (outline (path signal 100  -700 950  -700 -1500))
+      (pin Rect[T]Pad_1250x800_um 3 1016 0)
+      (pin Rect[T]Pad_1250x800_um 2 -1016 -950)
+      (pin Rect[T]Pad_1250x800_um 1 -1016 950)
+    )
+    (image "OAE_Parts:TerminalBlock_Altech_AK300-3_P5.00mm"
+      (outline (path signal 120  -3000 5000  -3000 -6000))
+      (outline (path signal 120  -3000 -6000  13000 -6000))
+      (outline (path signal 120  13000 -6000  13000 -5000))
+      (outline (path signal 120  13000 -5000  13500 -5500))
+      (outline (path signal 120  13500 -5500  13500 -3500))
+      (outline (path signal 120  13500 -3500  13000 -4000))
+      (outline (path signal 120  13000 -4000  13000 1500))
+      (outline (path signal 120  13000 1500  13500 1000))
+      (outline (path signal 120  13500 1000  13500 5000))
+      (outline (path signal 120  13500 5000  -3000 5000))
+      (outline (path signal 50  -3500 5500  14000 5500))
+      (outline (path signal 50  -3500 5500  -3500 -6500))
+      (outline (path signal 50  14000 -6500  14000 5500))
+      (outline (path signal 50  14000 -6500  -3500 -6500))
+      (pin Rect[A]Pad_1980x3960_um 1 0 0)
+      (pin Oval[A]Pad_1980x3960_um 2 5000 0)
+      (pin Oval[A]Pad_1980x3960_um 3 10000 0)
+    )
+    (image PartsLibraries:MountingHole_M3
+      (keepout "" (circle F.Cu 3200))
+      (keepout "" (circle B.Cu 3200))
+    )
+    (image "Diodes_THT:D_T-1_P5.08mm_Horizontal"
+      (outline (path signal 100  940 1300  940 -1300))
+      (outline (path signal 100  940 -1300  4140 -1300))
+      (outline (path signal 100  4140 -1300  4140 1300))
+      (outline (path signal 100  4140 1300  940 1300))
+      (outline (path signal 100  0 0  940 0))
+      (outline (path signal 100  5080 0  4140 0))
+      (outline (path signal 100  1420 1300  1420 -1300))
+      (outline (path signal 120  880 1180  880 1360))
+      (outline (path signal 120  880 1360  4200 1360))
+      (outline (path signal 120  4200 1360  4200 1180))
+      (outline (path signal 120  880 -1180  880 -1360))
+      (outline (path signal 120  880 -1360  4200 -1360))
+      (outline (path signal 120  4200 -1360  4200 -1180))
+      (outline (path signal 120  1420 1360  1420 -1360))
+      (outline (path signal 50  -1250 1650  -1250 -1650))
+      (outline (path signal 50  -1250 -1650  6350 -1650))
+      (outline (path signal 50  6350 -1650  6350 1650))
+      (outline (path signal 50  6350 1650  -1250 1650))
+      (pin Rect[A]Pad_2000x2000_um 1 0 0)
+      (pin Oval[A]Pad_2000x2000_um 2 5080 0)
+    )
+    (image OAE_Parts:TC4422AVPA
+      (outline (path signal 152.4  508 -8712.2  508 1092.2))
+      (outline (path signal 152.4  508 1193.8  7112 1193.8))
+      (outline (path signal 152.4  -482.6 -3048  508 -3048))
+      (outline (path signal 152.4  -482.6 -2032  -482.6 -3048))
+      (outline (path signal 152.4  508 -2032  -482.6 -2032))
+      (outline (path signal 152.4  508 -3048  508 -2032))
+      (outline (path signal 152.4  7112 -1574.8  7112 -965.2))
+      (outline (path signal 152.4  7112 -4114.8  7112 -3505.2))
+      (outline (path signal 152.4  508 -6045.2  508 -6654.8))
+      (outline (path signal 152.4  508 -3505.2  508 -4114.8))
+      (outline (path signal 152.4  508 -8712.2  7112 -8712.2))
+      (outline (path signal 152.4  7112 -6654.8  7112 -6045.2))
+      (outline (path signal 152.4  508 -1092.2  508 -1574.8))
+      (outline (path signal 152.4  508 -508  508 508))
+      (outline (path signal 152.4  508 508  -482.6 508))
+      (outline (path signal 152.4  -482.6 508  -482.6 -508))
+      (outline (path signal 152.4  -482.6 -508  508 -508))
+      (outline (path signal 152.4  508 -5588  508 -4572))
+      (outline (path signal 152.4  508 -4572  -482.6 -4572))
+      (outline (path signal 152.4  -482.6 -4572  -482.6 -5588))
+      (outline (path signal 152.4  -482.6 -5588  508 -5588))
+      (outline (path signal 152.4  508 -8128  508 -7112))
+      (outline (path signal 152.4  508 -7112  -482.6 -7137.4))
+      (outline (path signal 152.4  -482.6 -7137.4  -482.6 -8128))
+      (outline (path signal 152.4  -482.6 -8128  508 -8128))
+      (outline (path signal 152.4  7112 -7112  7112 -8128))
+      (outline (path signal 152.4  7112 -8128  8102.6 -8102.6))
+      (outline (path signal 152.4  8102.6 -8102.6  8102.6 -7112))
+      (outline (path signal 152.4  8102.6 -7112  7112 -7112))
+      (outline (path signal 152.4  7112 -4572  7112 -5588))
+      (outline (path signal 152.4  7112 -5588  8102.6 -5562.6))
+      (outline (path signal 152.4  8102.6 -5562.6  8102.6 -4572))
+      (outline (path signal 152.4  8102.6 -4572  7112 -4572))
+      (outline (path signal 152.4  7112 -2032  7112 -3048))
+      (outline (path signal 152.4  7112 -3048  8102.6 -3048))
+      (outline (path signal 152.4  8102.6 -3048  8102.6 -2032))
+      (outline (path signal 152.4  8102.6 -2032  7112 -2032))
+      (outline (path signal 152.4  7112 508  7112 -508))
+      (outline (path signal 152.4  7112 -508  8102.6 -508))
+      (outline (path signal 152.4  8102.6 -508  8102.6 508))
+      (outline (path signal 152.4  8102.6 508  7112 508))
+      (outline (path signal 152.4  508 -8712.2  7112 -8712.2))
+      (outline (path signal 152.4  7112 -8712.2  7112 1092.2))
+      (pin Rect[A]Pad_1485.9x1485.9_um (rotate 90) 1 0 0)
+      (pin Round[A]Pad_1485.9_um (rotate 90) 2 0 -2540)
+      (pin Round[A]Pad_1485.9_um (rotate 90) 3 0 -5080)
+      (pin Round[A]Pad_1485.9_um (rotate 90) 4 0 -7620)
+      (pin Round[A]Pad_1485.9_um (rotate 90) 5 7620 -7620)
+      (pin Round[A]Pad_1485.9_um (rotate 90) 6 7620 -5080)
+      (pin Round[A]Pad_1485.9_um (rotate 90) 7 7620 -2540)
+      (pin Round[A]Pad_1485.9_um (rotate 90) 8 7620 0)
+    )
+    (image "Housings_DIP:DIP-6_W7.62mm"
+      (outline (path signal 100  1635 1270  6985 1270))
+      (outline (path signal 100  6985 1270  6985 -6350))
+      (outline (path signal 100  6985 -6350  635 -6350))
+      (outline (path signal 100  635 -6350  635 270))
+      (outline (path signal 100  635 270  1635 1270))
+      (outline (path signal 120  2810 1330  1160 1330))
+      (outline (path signal 120  1160 1330  1160 -6410))
+      (outline (path signal 120  1160 -6410  6460 -6410))
+      (outline (path signal 120  6460 -6410  6460 1330))
+      (outline (path signal 120  6460 1330  4810 1330))
+      (outline (path signal 50  -1100 1550  -1100 -6600))
+      (outline (path signal 50  -1100 -6600  8700 -6600))
+      (outline (path signal 50  8700 -6600  8700 1550))
+      (outline (path signal 50  8700 1550  -1100 1550))
+      (pin Rect[A]Pad_1600x1600_um 1 0 0)
+      (pin Oval[A]Pad_1600x1600_um 4 7620 -5080)
+      (pin Oval[A]Pad_1600x1600_um 2 0 -2540)
+      (pin Oval[A]Pad_1600x1600_um 5 7620 -2540)
+      (pin Oval[A]Pad_1600x1600_um 3 0 -5080)
+      (pin Oval[A]Pad_1600x1600_um 6 7620 0)
+    )
+    (image "Connectors_JST:JST_XH_B03B-XH-A_03x2.50mm_Straight"
+      (outline (path signal 100  -2450 2350  -2450 -3400))
+      (outline (path signal 100  -2450 -3400  7450 -3400))
+      (outline (path signal 100  7450 -3400  7450 2350))
+      (outline (path signal 100  7450 2350  -2450 2350))
+      (outline (path signal 50  -2950 2850  -2950 -3900))
+      (outline (path signal 50  -2950 -3900  7950 -3900))
+      (outline (path signal 50  7950 -3900  7950 2850))
+      (outline (path signal 50  7950 2850  -2950 2850))
+      (outline (path signal 120  -2550 2450  -2550 -3500))
+      (outline (path signal 120  -2550 -3500  7550 -3500))
+      (outline (path signal 120  7550 -3500  7550 2450))
+      (outline (path signal 120  7550 2450  -2550 2450))
+      (outline (path signal 120  750 2450  750 1700))
+      (outline (path signal 120  750 1700  4250 1700))
+      (outline (path signal 120  4250 1700  4250 2450))
+      (outline (path signal 120  4250 2450  750 2450))
+      (outline (path signal 120  -2550 2450  -2550 1700))
+      (outline (path signal 120  -2550 1700  -750 1700))
+      (outline (path signal 120  -750 1700  -750 2450))
+      (outline (path signal 120  -750 2450  -2550 2450))
+      (outline (path signal 120  5750 2450  5750 1700))
+      (outline (path signal 120  5750 1700  7550 1700))
+      (outline (path signal 120  7550 1700  7550 2450))
+      (outline (path signal 120  7550 2450  5750 2450))
+      (outline (path signal 120  -2550 200  -1800 200))
+      (outline (path signal 120  -1800 200  -1800 -2750))
+      (outline (path signal 120  -1800 -2750  2500 -2750))
+      (outline (path signal 120  7550 200  6800 200))
+      (outline (path signal 120  6800 200  6800 -2750))
+      (outline (path signal 120  6800 -2750  2500 -2750))
+      (outline (path signal 120  -350 2750  -2850 2750))
+      (outline (path signal 120  -2850 2750  -2850 250))
+      (outline (path signal 100  -350 2750  -2850 2750))
+      (outline (path signal 100  -2850 2750  -2850 250))
+      (pin Rect[A]Pad_1750x1750_um 1 0 0)
+      (pin Round[A]Pad_1750_um 2 2500 0)
+      (pin Round[A]Pad_1750_um 3 5000 0)
+    )
+    (image "Housings_DIP:DIP-14_W7.62mm_Socket::1"
+      (outline (path signal 50  9150 1600  -1550 1600))
+      (outline (path signal 50  9150 -16850  9150 1600))
+      (outline (path signal 50  -1550 -16850  9150 -16850))
+      (outline (path signal 50  -1550 1600  -1550 -16850))
+      (outline (path signal 120  8950 1390  -1330 1390))
+      (outline (path signal 120  8950 -16630  8950 1390))
+      (outline (path signal 120  -1330 -16630  8950 -16630))
+      (outline (path signal 120  -1330 1390  -1330 -16630))
+      (outline (path signal 120  6460 1330  4810 1330))
+      (outline (path signal 120  6460 -16570  6460 1330))
+      (outline (path signal 120  1160 -16570  6460 -16570))
+      (outline (path signal 120  1160 1330  1160 -16570))
+      (outline (path signal 120  2810 1330  1160 1330))
+      (outline (path signal 100  8890 1330  -1270 1330))
+      (outline (path signal 100  8890 -16570  8890 1330))
+      (outline (path signal 100  -1270 -16570  8890 -16570))
+      (outline (path signal 100  -1270 1330  -1270 -16570))
+      (outline (path signal 100  635 270  1635 1270))
+      (outline (path signal 100  635 -16510  635 270))
+      (outline (path signal 100  6985 -16510  635 -16510))
+      (outline (path signal 100  6985 1270  6985 -16510))
+      (outline (path signal 100  1635 1270  6985 1270))
+      (pin Oval[A]Pad_1600x1600_um 14 7620 0)
+      (pin Oval[A]Pad_1600x1600_um 7 0 -15240)
+      (pin Oval[A]Pad_1600x1600_um 13 7620 -2540)
+      (pin Oval[A]Pad_1600x1600_um 6 0 -12700)
+      (pin Oval[A]Pad_1600x1600_um 12 7620 -5080)
+      (pin Oval[A]Pad_1600x1600_um 5 0 -10160)
+      (pin Oval[A]Pad_1600x1600_um 11 7620 -7620)
+      (pin Oval[A]Pad_1600x1600_um 4 0 -7620)
+      (pin Oval[A]Pad_1600x1600_um 10 7620 -10160)
+      (pin Oval[A]Pad_1600x1600_um 3 0 -5080)
+      (pin Oval[A]Pad_1600x1600_um 9 7620 -12700)
+      (pin Oval[A]Pad_1600x1600_um 2 0 -2540)
+      (pin Oval[A]Pad_1600x1600_um 8 7620 -15240)
+      (pin Rect[A]Pad_1600x1600_um 1 0 0)
+    )
+    (image OAE_Parts:PowerConnectorRound_M3
+      (pin Round[A]Pad_6000_um 1 0 0)
+    )
+    (image "OAE_Parts:RJ45-shielded-Molex"
+      (outline (path signal 120  -3200 -13000  12200 -13000))
+      (outline (path signal 120  12200 3800  12200 -5000))
+      (outline (path signal 120  12200 3800  -3200 3800))
+      (outline (path signal 120  -3200 3800  -3200 -5000))
+      (outline (path signal 120  12200 -11000  12200 -13000))
+      (outline (path signal 120  -3200 -11000  -3200 -13000))
+      (outline (path signal 50  -3600 4100  12500 4100))
+      (outline (path signal 50  -3600 4100  -3600 -13300))
+      (outline (path signal 50  12500 -13300  12500 4100))
+      (outline (path signal 50  12500 -13300  -3600 -13300))
+      (pin Rect[A]Pad_1500x1500_um 1 0 0)
+      (pin Round[A]Pad_1500_um 2 1270 2540)
+      (pin Round[A]Pad_1500_um 3 2540 0)
+      (pin Round[A]Pad_1500_um 4 3810 2540)
+      (pin Round[A]Pad_1500_um 5 5080 0)
+      (pin Round[A]Pad_1500_um 6 6350 2540)
+      (pin Round[A]Pad_1500_um 7 7620 0)
+      (pin Round[A]Pad_1500_um 8 8890 2540)
+      (pin Round[A]Pad_2200_um 9 -3355 -9400)
+      (pin Round[A]Pad_2200_um 9@1 12245 -9400)
+      (keepout "" (circle F.Cu 3250 10160 -6350))
+      (keepout "" (circle B.Cu 3250 10160 -6350))
+      (keepout "" (circle F.Cu 3250 -1270 -6350))
+      (keepout "" (circle B.Cu 3250 -1270 -6350))
+    )
+    (padstack Round[A]Pad_1485.9_um
+      (shape (circle F.Cu 1485.9))
+      (shape (circle B.Cu 1485.9))
+      (attach off)
+    )
+    (padstack Round[A]Pad_1500_um
+      (shape (circle F.Cu 1500))
+      (shape (circle B.Cu 1500))
+      (attach off)
+    )
+    (padstack Round[A]Pad_1600_um
+      (shape (circle F.Cu 1600))
+      (shape (circle B.Cu 1600))
+      (attach off)
+    )
+    (padstack Round[A]Pad_1750_um
+      (shape (circle F.Cu 1750))
+      (shape (circle B.Cu 1750))
+      (attach off)
+    )
+    (padstack Round[A]Pad_2200_um
+      (shape (circle F.Cu 2200))
+      (shape (circle B.Cu 2200))
+      (attach off)
+    )
+    (padstack Round[A]Pad_6000_um
+      (shape (circle F.Cu 6000))
+      (shape (circle B.Cu 6000))
+      (attach off)
+    )
+    (padstack Oval[A]Pad_1600x1600_um
+      (shape (path F.Cu 1600  0 0  0 0))
+      (shape (path B.Cu 1600  0 0  0 0))
+      (attach off)
+    )
+    (padstack Oval[A]Pad_1800x1800_um
+      (shape (path F.Cu 1800  0 0  0 0))
+      (shape (path B.Cu 1800  0 0  0 0))
+      (attach off)
+    )
+    (padstack Oval[A]Pad_1980x3960_um
+      (shape (path F.Cu 1980  0 -990  0 990))
+      (shape (path B.Cu 1980  0 -990  0 990))
+      (attach off)
+    )
+    (padstack Oval[A]Pad_2000x2000_um
+      (shape (path F.Cu 2000  0 0  0 0))
+      (shape (path B.Cu 2000  0 0  0 0))
+      (attach off)
+    )
+    (padstack Rect[A]Pad_2000x2000_um
+      (shape (rect F.Cu -1000 -1000 1000 1000))
+      (shape (rect B.Cu -1000 -1000 1000 1000))
+      (attach off)
+    )
+    (padstack Rect[T]Pad_1250x800_um
+      (shape (rect F.Cu -625 -400 625 400))
+      (attach off)
+    )
+    (padstack Rect[A]Pad_1485.9x1485.9_um
+      (shape (rect F.Cu -742.95 -742.95 742.95 742.95))
+      (shape (rect B.Cu -742.95 -742.95 742.95 742.95))
+      (attach off)
+    )
+    (padstack Rect[A]Pad_1500x1500_um
+      (shape (rect F.Cu -750 -750 750 750))
+      (shape (rect B.Cu -750 -750 750 750))
+      (attach off)
+    )
+    (padstack Rect[A]Pad_1600x1600_um
+      (shape (rect F.Cu -800 -800 800 800))
+      (shape (rect B.Cu -800 -800 800 800))
+      (attach off)
+    )
+    (padstack Rect[A]Pad_1750x1750_um
+      (shape (rect F.Cu -875 -875 875 875))
+      (shape (rect B.Cu -875 -875 875 875))
+      (attach off)
+    )
+    (padstack Rect[A]Pad_1800x1800_um
+      (shape (rect F.Cu -900 -900 900 900))
+      (shape (rect B.Cu -900 -900 900 900))
+      (attach off)
+    )
+    (padstack Rect[A]Pad_1980x3960_um
+      (shape (rect F.Cu -990 -1980 990 1980))
+      (shape (rect B.Cu -990 -1980 990 1980))
+      (attach off)
+    )
+    (padstack "Via[0-1]_1500:1000_um"
+      (shape (circle F.Cu 1500))
+      (shape (circle B.Cu 1500))
+      (attach off)
+    )
+  )
+  (network
+    (net "Net-(IC1-Pad2)"
+      (pins R10-2 IC1-2 U2-4)
+    )
+    (net "Net-(IC2-Pad2)"
+      (pins R12-2 U4-4 IC2-2)
+    )
+    (net "Net-(IC3-Pad2)"
+      (pins U6-4 R14-2 IC3-2)
+    )
+    (net "Net-(IC4-Pad2)"
+      (pins R16-2 U8-4 IC4-2)
+    )
+    (net DC_IN
+      (pins U201-14 U301-14 J1-4 U401-14 U501-14)
+    )
+    (net DC_GND
+      (pins U201-1 U301-1 J1-5 U401-1 U501-1)
+    )
+    (net ARD_GND
+      (pins U2-2 J101-2 U8-2 U6-2 R1-2 U4-2 J1-8 J7-1 J7-3 J7-5 J7-7)
+    )
+    (net "Net-(C17-Pad1)"
+      (pins R3-2 C17-1 D1-1 R10-1 U2-6)
+    )
+    (net "Net-(C19-Pad1)"
+      (pins R12-1 C19-1 U4-6 R5-2 D2-1)
+    )
+    (net "Net-(C21-Pad1)"
+      (pins U6-6 C21-1 R14-1 R7-2 D3-1)
+    )
+    (net "Net-(C23-Pad1)"
+      (pins R16-1 C23-1 D4-1 U8-6 R9-2)
+    )
+    (net ARD_PWM_A
+      (pins R2-1 C25-2 J7-8)
+    )
+    (net ARD_PWM_B
+      (pins R4-1 C26-2 J7-6)
+    )
+    (net ARD_PWM_C
+      (pins C27-2 R6-1 J7-2)
+    )
+    (net ARD_PWM_D
+      (pins C28-2 R8-1 J7-4)
+    )
+    (net "Net-(C25-Pad1)"
+      (pins R2-2 U2-1 C25-1)
+    )
+    (net "Net-(C26-Pad1)"
+      (pins R4-2 U4-1 C26-1)
+    )
+    (net "Net-(C27-Pad1)"
+      (pins C27-1 U6-1 R6-2)
+    )
+    (net "Net-(C28-Pad1)"
+      (pins C28-1 U8-1 R8-2)
+    )
+    (net ARD_CUR
+      (pins J101-1 J1-1)
+    )
+    (net ARD_VCC
+      (pins J2-1 J101-3 J1-7)
+    )
+    (net ARD_TEMP
+      (pins J2-2 J1-6)
+    )
+    (net "Net-(J2-Pad3)"
+      (pins J2-3 R1-1)
+    )
+    (net /PsuSwitchModule.Switch.1/GND_ISO
+      (pins C2-2 C18-2 C1-2 U201-8 D201-1 C17-2 C3-1 D1-2 R11-2 IC1-4 IC1-5 U2-5)
+    )
+    (net /PsuSwitchModule.Switch.1/DRV_SIG
+      (pins R204-1 J201-2 R203-1)
+    )
+    (net /PsuSwitchModule.Switch.2/GND_ISO
+      (pins D301-1 U301-8 C5-2 C6-2 C7-1 C19-2 C20-2 R13-2 U4-5 D2-2 IC2-4 IC2-5)
+    )
+    (net /PsuSwitchModule.Switch.2/DRV_SIG
+      (pins R304-1 R303-1 J301-2)
+    )
+    (net /PsuSwitchModule.Switch.3/GND_ISO
+      (pins C10-2 D401-1 U6-5 C9-2 C11-1 C21-2 C22-2 R15-2 D3-2 IC3-4 IC3-5 U401-8)
+    )
+    (net /PsuSwitchModule.Switch.3/DRV_SIG
+      (pins R404-1 R403-1 J401-2)
+    )
+    (net /PsuSwitchModule.Switch.4/GND_ISO
+      (pins D501-1 R17-2 C23-2 D4-2 C24-2 C14-2 U8-5 C13-2 C15-1 IC4-4 IC4-5 U501-8)
+    )
+    (net /PsuSwitchModule.Switch.4/DRV_SIG
+      (pins R504-1 R503-1 J501-2)
+    )
+    (net Earth
+      (pins J201-1 J501-1 J102-1 J1-9 J1-9@1 J7-9 J7-9@1 J301-1 J401-1)
+    )
+    (net "Net-(IC1-Pad3)"
+      (pins IC1-3)
+    )
+    (net "Net-(IC2-Pad3)"
+      (pins IC2-3)
+    )
+    (net "Net-(IC3-Pad3)"
+      (pins IC3-3)
+    )
+    (net "Net-(IC4-Pad3)"
+      (pins IC4-3)
+    )
+    (net "Net-(J1-Pad2)"
+      (pins J1-2)
+    )
+    (net "Net-(J1-Pad3)"
+      (pins J1-3)
+    )
+    (net "Net-(U2-Pad3)"
+      (pins U2-3)
+    )
+    (net "Net-(U4-Pad3)"
+      (pins U4-3)
+    )
+    (net "Net-(U6-Pad3)"
+      (pins U6-3)
+    )
+    (net "Net-(U8-Pad3)"
+      (pins U8-3)
+    )
+    (net /PsuSwitchModule.Switch.1/+15V
+      (pins C2-1 C18-1 C1-1 R201-1 R3-1 U201-9 IC1-1 IC1-8)
+    )
+    (net /PsuSwitchModule.Switch.2/+15V
+      (pins U301-9 C5-1 C6-1 C20-1 R5-1 IC2-1 IC2-8 R301-1)
+    )
+    (net /PsuSwitchModule.Switch.3/+15V
+      (pins C10-1 C9-1 C22-1 R7-1 IC3-1 IC3-8 R401-1 U401-9)
+    )
+    (net /PsuSwitchModule.Switch.4/+15V
+      (pins C24-1 C14-1 R9-1 C13-1 IC4-1 IC4-8 R501-1 U501-9)
+    )
+    (net "/PsuSwitchModule.Switch.1/-5V"
+      (pins R201-2 R202-1 J201-3)
+    )
+    (net "/PsuSwitchModule.Switch.2/-5V"
+      (pins J301-3 R301-2 R302-1)
+    )
+    (net "/PsuSwitchModule.Switch.3/-5V"
+      (pins J401-3 R401-2 R402-1)
+    )
+    (net "/PsuSwitchModule.Switch.4/-5V"
+      (pins J501-3 R501-2 R502-1)
+    )
+    (net "/PsuSwitchModule.Switch.1/-15V"
+      (pins R202-2 U201-11)
+    )
+    (net "/PsuSwitchModule.Switch.2/-15V"
+      (pins U301-11 R302-2)
+    )
+    (net "/PsuSwitchModule.Switch.3/-15V"
+      (pins R402-2 U401-11)
+    )
+    (net "/PsuSwitchModule.Switch.4/-15V"
+      (pins R502-2 U501-11)
+    )
+    (net "Net-(C3-Pad2)"
+      (pins D202-1 D201-3 R203-2 C3-2 R11-1 IC1-6 IC1-7)
+    )
+    (net "Net-(C7-Pad2)"
+      (pins R303-2 D302-1 D301-3 C7-2 R13-1 IC2-6 IC2-7)
+    )
+    (net "Net-(C11-Pad2)"
+      (pins R403-2 D402-1 D401-3 C11-2 R15-1 IC3-6 IC3-7)
+    )
+    (net "Net-(C15-Pad2)"
+      (pins R503-2 D502-1 D501-3 R17-1 C15-2 IC4-6 IC4-7)
+    )
+    (net "Net-(D202-Pad2)"
+      (pins D202-2 R204-2)
+    )
+    (net "Net-(D302-Pad2)"
+      (pins R304-2 D302-2)
+    )
+    (net "Net-(D402-Pad2)"
+      (pins R404-2 D402-2)
+    )
+    (net "Net-(D502-Pad2)"
+      (pins R504-2 D502-2)
+    )
+    (net "Net-(D201-Pad2)"
+      (pins D201-2)
+    )
+    (net "Net-(D301-Pad2)"
+      (pins D301-2)
+    )
+    (net "Net-(D401-Pad2)"
+      (pins D401-2)
+    )
+    (net "Net-(D501-Pad2)"
+      (pins D501-2)
+    )
+    (class kicad_default "" /PsuSwitchModule.Switch.1/+15V "/PsuSwitchModule.Switch.1/-15V"
+      "/PsuSwitchModule.Switch.1/-5V" /PsuSwitchModule.Switch.1/DRV_SIG /PsuSwitchModule.Switch.1/GND_ISO
+      /PsuSwitchModule.Switch.2/+15V "/PsuSwitchModule.Switch.2/-15V" "/PsuSwitchModule.Switch.2/-5V"
+      /PsuSwitchModule.Switch.2/DRV_SIG /PsuSwitchModule.Switch.2/GND_ISO
+      /PsuSwitchModule.Switch.3/+15V "/PsuSwitchModule.Switch.3/-15V" "/PsuSwitchModule.Switch.3/-5V"
+      /PsuSwitchModule.Switch.3/DRV_SIG /PsuSwitchModule.Switch.3/GND_ISO
+      /PsuSwitchModule.Switch.4/+15V "/PsuSwitchModule.Switch.4/-15V" "/PsuSwitchModule.Switch.4/-5V"
+      /PsuSwitchModule.Switch.4/DRV_SIG /PsuSwitchModule.Switch.4/GND_ISO
+      ARD_CUR ARD_GND ARD_PWM_A ARD_PWM_B ARD_PWM_C ARD_PWM_D ARD_TEMP ARD_VCC
+      DC_GND DC_IN Earth "Net-(C11-Pad2)" "Net-(C15-Pad2)" "Net-(C17-Pad1)"
+      "Net-(C19-Pad1)" "Net-(C21-Pad1)" "Net-(C23-Pad1)" "Net-(C25-Pad1)"
+      "Net-(C26-Pad1)" "Net-(C27-Pad1)" "Net-(C28-Pad1)" "Net-(C3-Pad2)" "Net-(C7-Pad2)"
+      "Net-(D201-Pad2)" "Net-(D202-Pad2)" "Net-(D301-Pad2)" "Net-(D302-Pad2)"
+      "Net-(D401-Pad2)" "Net-(D402-Pad2)" "Net-(D501-Pad2)" "Net-(D502-Pad2)"
+      "Net-(IC1-Pad2)" "Net-(IC1-Pad3)" "Net-(IC2-Pad2)" "Net-(IC2-Pad3)"
+      "Net-(IC3-Pad2)" "Net-(IC3-Pad3)" "Net-(IC4-Pad2)" "Net-(IC4-Pad3)"
+      "Net-(J1-Pad2)" "Net-(J1-Pad3)" "Net-(J2-Pad3)" "Net-(U2-Pad3)" "Net-(U4-Pad3)"
+      "Net-(U6-Pad3)" "Net-(U8-Pad3)"
+      (circuit
+        (use_via Via[0-1]_1500:1000_um)
+      )
+      (rule
+        (width 1000)
+        (clearance 400.1)
+      )
+    )
+  )
+  (wiring
+  )
+)

Diferenças do arquivo suprimidas por serem muito extensas
+ 2932 - 3892
MLI/Modular/PsuSwitchModule/PsuSwitchModule.kicad_pcb


Diferenças do arquivo suprimidas por serem muito extensas
+ 4815 - 5775
MLI/Modular/PsuSwitchModule/PsuSwitchModule.kicad_pcb-bak


+ 84 - 0
MLI/Modular/PsuSwitchModule/PsuSwitchModule.rules

@@ -0,0 +1,84 @@
+
+(rules PCB PsuSwitchModule
+  (snap_angle 
+    fortyfive_degree
+  )
+  (autoroute_settings
+    (fanout off)
+    (autoroute on)
+    (postroute on)
+    (vias on)
+    (via_costs 50)
+    (plane_via_costs 5)
+    (start_ripup_costs 100)
+    (start_pass_no 2655)
+    (layer_rule F.Cu
+      (active on)
+      (preferred_direction horizontal)
+      (preferred_direction_trace_costs 1.0)
+      (against_preferred_direction_trace_costs 2.6)
+    )
+    (layer_rule B.Cu
+      (active on)
+      (preferred_direction vertical)
+      (preferred_direction_trace_costs 1.0)
+      (against_preferred_direction_trace_costs 1.6)
+    )
+  )
+  (rule
+    (width 1000.0)
+    (clear 400.2)
+    (clear 500.0 (type smd_to_turn_gap))
+    (clear 100.0 (type smd_smd))
+  )
+  (padstack "Via[0-1]_1500:1000_um"
+    (shape
+      (circle F.Cu 1500.0 0.0 0.0)
+    )
+    (shape
+      (circle B.Cu 1500.0 0.0 0.0)
+    )
+    (attach off)
+  )
+  (via 
+    "Via[0-1]_1500:1000_um" "Via[0-1]_1500:1000_um" default
+  )
+  (via 
+    "Via[0-1]_1500:1000_um-kicad_default" "Via[0-1]_1500:1000_um" "kicad_default"
+  )
+  (via_rule
+    default "Via[0-1]_1500:1000_um"
+  )
+  (via_rule
+    "kicad_default" "Via[0-1]_1500:1000_um-kicad_default"
+  )
+  (class default
+    (clearance_class default)
+    (via_rule default)
+    (rule
+      (width 1000.0)
+    )
+    (circuit 
+      (use_layer F.Cu B.Cu)
+    )
+  )
+  (class "kicad_default"
+    Earth "Net-(IC1-Pad2)" "Net-(IC2-Pad2)" "Net-(IC3-Pad2)" "Net-(IC4-Pad2)" "DC_IN" "DC_GND" "ARD_GND"
+    "Net-(C17-Pad1)" "Net-(C19-Pad1)" "Net-(C21-Pad1)" "Net-(C23-Pad1)" "ARD_PWM_A" "ARD_PWM_B" "ARD_PWM_C" "ARD_PWM_D"
+    "Net-(C25-Pad1)" "Net-(C26-Pad1)" "Net-(C27-Pad1)" "Net-(C28-Pad1)" "ARD_CUR" "ARD_VCC" "ARD_TEMP" "Net-(J2-Pad3)"
+    "/PsuSwitchModule.Switch.1/GND_ISO" "/PsuSwitchModule.Switch.1/DRV_SIG" "/PsuSwitchModule.Switch.2/GND_ISO" "/PsuSwitchModule.Switch.2/DRV_SIG" "/PsuSwitchModule.Switch.3/GND_ISO" "/PsuSwitchModule.Switch.3/DRV_SIG" "/PsuSwitchModule.Switch.4/GND_ISO" "/PsuSwitchModule.Switch.4/DRV_SIG"
+    "Net-(IC1-Pad3)" "Net-(IC2-Pad3)" "Net-(IC3-Pad3)" "Net-(IC4-Pad3)" "Net-(J1-Pad2)" "Net-(J1-Pad3)" "Net-(U2-Pad3)" "Net-(U4-Pad3)"
+    "Net-(U6-Pad3)" "Net-(U8-Pad3)" /PsuSwitchModule.Switch.1/+15V /PsuSwitchModule.Switch.2/+15V /PsuSwitchModule.Switch.3/+15V /PsuSwitchModule.Switch.4/+15V "/PsuSwitchModule.Switch.1/-5V" "/PsuSwitchModule.Switch.2/-5V"
+    "/PsuSwitchModule.Switch.3/-5V" "/PsuSwitchModule.Switch.4/-5V" "/PsuSwitchModule.Switch.1/-15V" "/PsuSwitchModule.Switch.2/-15V" "/PsuSwitchModule.Switch.3/-15V" "/PsuSwitchModule.Switch.4/-15V" "Net-(C3-Pad2)" "Net-(C7-Pad2)"
+    "Net-(C11-Pad2)" "Net-(C15-Pad2)" "Net-(D202-Pad2)" "Net-(D302-Pad2)" "Net-(D402-Pad2)" "Net-(D502-Pad2)" "Net-(D201-Pad2)" "Net-(D301-Pad2)"
+    "Net-(D401-Pad2)" "Net-(D501-Pad2)"
+    (clearance_class "kicad_default")
+    (via_rule kicad_default)
+    (rule
+      (width 1000.0)
+    )
+    (circuit 
+      (use_layer F.Cu B.Cu)
+    )
+  )
+)

+ 4 - 4
MLI/Modular/PsuSwitchModule/PsuSwitchModule.sch

@@ -5,12 +5,12 @@ $Descr A4 11693 8268
 encoding utf-8
 Sheet 1 5
 Title "Power Module (Control Board)"
-Date "2020-02-19"
-Rev "Release 4.1a"
+Date "2020-11-24"
+Rev "Release 4.2"
 Comp "Enertechnos Ltd"
 Comment1 "FOR APPROVAL"
-Comment2 ""
-Comment3 ""
+Comment2 "Extra Capicitor Removed"
+Comment3 "Ground planes connected to Earth instead of DC_GND"
 Comment4 ""
 $EndDescr
 Text GLabel 2250 2850 0    60   Output ~ 0

+ 3 - 4
MLI/Modular/PsuSwitchModule/PsuSwitchModule.sch-bak

@@ -1,6 +1,5 @@
 EESchema Schematic File Version 4
-LIBS:PsuSwitchModule-cache
-EELAYER 29 0
+EELAYER 30 0
 EELAYER END
 $Descr A4 11693 8268
 encoding utf-8
@@ -33,7 +32,7 @@ ARD_PWM_A
 Text GLabel 4550 1900 0    60   UnSpc ~ 0
 ARD_GND
 $Comp
-L OAE.Parts:RJ45 J1
+L PsuSwitchModule-rescue:RJ45-OAE.Parts J1
 U 1 1 59526541
 P 2700 1850
 F 0 "J1" H 2900 2350 50  0000 C CNN
@@ -217,7 +216,7 @@ ARD_GND
 Text GLabel 2250 3350 0    60   UnSpc ~ 0
 ARD_GND
 $Comp
-L OAE.Parts:RJ45 J7
+L PsuSwitchModule-rescue:RJ45-OAE.Parts J7
 U 1 1 59A7EBD8
 P 2700 3100
 F 0 "J7" H 2900 3600 50  0000 C CNN

Diferenças do arquivo suprimidas por serem muito extensas
+ 2659 - 0
MLI/Modular/PsuSwitchModule/PsuSwitchModule.ses


Diferenças do arquivo suprimidas por serem muito extensas
+ 81263 - 259
MLI/Modular/PsuSwitchModule/fp-info-cache